Datasheet

System Integration Module (SIM)
MC68HC908GP32 Data Sheet, Rev. 10
172 Freescale Semiconductor
14.7.1 SIM Break Status Register
The SIM break status register (SBSR) contains a flag to indicate that a break caused an exit from wait
mode.
SBSW — SIM Break Stop/Wait
SBSW can be read within the break state SWI routine. The user can modify the return address on the
stack by subtracting one from it.
1 = Wait mode was exited by break interrupt.
0 = Wait mode was not exited by break interrupt.
14.7.2 SIM Reset Status Register
The SRSR register contains flags that show the source of the last reset. The status register will
automatically clear after reading SRSR. A power-on reset sets the POR bit and clears all other bits in the
register. All other reset sources set the individual flag bits but do not clear the register. More than one
reset source can be flagged at any time depending on the conditions at the time of the internal or external
reset. For example, the POR and LVI bit can both be set if the power supply has a slow rise time.
POR — Power-On Reset Bit
1 = Last reset caused by POR circuit
0 = Read of SRSR
PIN — External Reset Bit
1 = Last reset caused by external reset pin (
RST)
0 = POR or read of SRSR
COP — Computer Operating Properly Reset Bit
1 = Last reset caused by COP counter
0 = POR or read of SRSR
Address: $FE00
Bit 7654321Bit 0
Read:
RRRRRR
SBSW
R
Write: Note
Reset: 0
R = Reserved
Note: Writing a logic 0 clears SBSW.
Figure 14-20. SIM Break Status Register (SBSR)
Address: $FE01
Bit 7654321Bit 0
Read: POR PIN COP ILOP ILAD MODRST LVI 0
Write:
Reset:10000000
= Unimplemented
Figure 14-21. SIM Reset Status Register (SRSR)