Datasheet

System Integration Module (SIM)
MC68HC908GP32 Data Sheet, Rev. 10
158 Freescale Semiconductor
Figure 14-1. SIM Block Diagram
Addr. Register Name Bit 7 654321Bit 0
$FE00
SIM Break Status Register
(SBSR)
Read:
RRRRRR
SBSW
R
Write: Note
Reset: 0
Note: Writing a logic 0 clears SBSW.
$FE01
SIM Reset Status Register
(SRSR)
Read: POR PIN COP ILOP ILAD MODRST LVI 0
Write:
POR: 10000000
$FE02
SIM Upper Byte Address
Register (SUBAR)
Read:
RRRRRRRR
Write:
Reset:
= Unimplemented R = Reserved
Figure 14-2. SIM I/O Register Summary
STOP/WAIT
CLOCK
CONTROL
CLOCK GENERATORS
POR CONTROL
RESET PIN CONTROL
SIM RESET STATUS REGISTER
INTERRUPT CONTROL
AND PRIORITY DECODE
MODULE STOP
MODULE WAIT
CPU STOP (FROM CPU)
CPU WAIT (FROM CPU)
SIMOSCEN (TO CGM)
CGMOUT (FROM CGM)
INTERNAL CLOCKS
MASTER
RESET
CONTROL
RESET
PIN LOGIC
LVI (FROM LVI MODULE)
ILLEGAL OPCODE (FROM CPU)
ILLEGAL ADDRESS (FROM ADDRESS
MAP DECODERS)
COP (FROM COP MODULE)
INTERRUPT SOURCES
CPU INTERFACE
RESET
CONTROL
SIM
COUNTER
COP CLOCK
CGMXCLK (FROM CGM)
÷ 2
V
DD
INTERNAL
PULLUP
DEVICE