Datasheet

Port C
MC68HC908GP32 Data Sheet, Rev. 10
Freescale Semiconductor 123
Figure 12-11 shows the port C I/O logic.
NOTE
For those devices packaged in a 40-pin dual in-line package and 42-pin
shrink dual in-line package, PTC5 and PTC6 are connected to ground
internally. DDRC5 and DDRC6 should be set to a 0 to configure PTC5 and
PTC6 as inputs.
Figure 12-11. Port C I/O Circuit
When bit DDRCx is a logic 1, reading address $0002 reads the PTCx data latch. When bit DDRCx is a
logic 0, reading address $0002 reads the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit. Table 12-4 summarizes the operation of the port C pins.
Table 12-4. Port C Pin Functions
PTCPUE Bit DDRC Bit PTC Bit I/O Pin Mode
Accesses to DDRC Accesses to PTC
Read/Write Read Write
10
X
(1)
Input, V
DD
(4)
DDRC6–DDRC0 Pin
PTC6–PTC0
(3)
00X
Input, Hi-Z
(2)
DDRC6–DDRC0 Pin
PTC6–PTC0
(3)
X 1 X Output DDRC6–DDRC0 PTC6–PTC0 PTC6–PTC0
Notes:
1. X = Don’t care
2. Hi-Z = High impedance
3. Writing affects data register, but does not affect input.
4. I/O pin pulled up to V
DD
by internal pullup device.
READ DDRC ($0006)
WRITE DDRC ($0006)
RESET
WRITE PTC ($0002)
READ PTC ($0002)
PTCx
DDRCx
PTCx
INTERNAL DATA BUS
V
DD
PTCPUEx
INTERNAL
PULLUP
DEVICE