Datasheet

Byte Data Link Controller (BDLC)
MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6
344 Freescale Semiconductor
Figure 27-6. J1850 VPW Symbols with Nominal Symbol Times
Start-of-Frame Symbol (SOF)
The SOF symbol is defined as passive-to-active transition followed by an active period 200 μs in length
(See Figure 27-6. J1850 VPW Symbols with Nominal Symbol Times (d)). This allows the data bytes
which follow the SOF symbol to begin with a passive bit, regardless of whether it is a logic 1 or a logic 0.
End-of-Data Symbol (EOD)
The EOD symbol is defined as an active-to-passive transition followed by a passive period 200 μs in
length (See Figure 27-6. J1850 VPW Symbols with Nominal Symbol Times (e)).
End-of-Frame Symbol (EOF)
The EOF symbol is defined as an active-to-passive transition followed by a passive period 280 μs in
length (See Figure 27-6. J1850 VPW Symbols with Nominal Symbol Times (f)). If no IFR byte is
transmitted after an EOD symbol is transmitted, after another 80 μs the EOD becomes an EOF,
indicating completion of the message.
Inter-Frame Separation Symbol (IFS)
The IFS symbol is defined as a passive period 300 μs in length. The 20-μs IFS symbol contains no
transition, since when used it always appends to an EOF symbol (See Figure 27-6. J1850 VPW
Symbols with Nominal Symbol Times (g)).
128 μs
ACTIVE
PASSIVE
64 μs
OR
(A) LOGIC 0
128 μs
ACTIVE
PASSIVE
64 μs
OR
(B) LOGIC 1
200 μs
ACTIVE
PASSIVE
(D) START OF FRAME
ACTIVE
PASSIVE
(F) END OF FRAME
≥ 240 μs
(C) BREAK
200 μs
(E) END OF DATA
280 μs
(G) INTER-FRAME
20 μs
300 μs
IDLE > 300 μs
(H) IDLE
SEPARATION