Datasheet

Serial Communications Interface (SCI)
MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6
194 Freescale Semiconductor
0 = Idle character bit count begins after start bit
PEN — Parity Enable Bit
This read/write bit enables the SCI parity function. (See Table 18-8). When enabled, the parity function
inserts a parity bit in the most significant bit position. (See Table 18-7). Reset clears the PEN bit.
1 = Parity function enabled
0 = Parity function disabled
PTY — Parity Bit
This read/write bit determines whether the SCI generates and checks for odd parity or even parity.
(See Table 18-8). Reset clears the PTY bit.
1 = Odd parity
0 = Even parity
NOTE
Changing the PTY bit in the middle of a transmission or reception can
generate a parity error.
18.8.2 SCI Control Register 2
SCI control register 2:
• Enables the following CPU interrupt requests:
– Enables the SCTE bit to generate transmitter CPU interrupt requests
– Enables the TC bit to generate transmitter CPU interrupt requests
– Enables the SCRF bit to generate receiver CPU interrupt requests
– Enables the IDLE bit to generate receiver CPU interrupt requests
• Enables the transmitter
• Enables the receiver
• Enables SCI wakeup
• Transmits SCI break characters
Table 18-8. Character Format Selection
Control Bits Character Format
M PEN:PTY
Start
Bits
Data
Bits
Parity
Stop
Bits
Character
Length
00X 18None1 10 Bits
10X 19None1 11 Bits
010 17Even1 10 Bits
011 17Odd1 10 Bits
110 18Even1 11 Bits
111 18Odd1 11 Bits