Datasheet

SIM Bus Clock Control and Generation
MC68HC908AP Family Data Sheet, Rev. 4
Freescale Semiconductor 99
7.2 SIM Bus Clock Control and Generation
The bus clock generator provides system clock signals for the CPU and peripherals on the MCU. The
system clocks are generated from an incoming clock, CGMOUT, as shown in Figure 7-3. This clock can
come from either an external oscillator or from the on-chip PLL. (See Chapter 6 Clock Generator Module
(CGM).)
Figure 7-3. CGM Clock Signals
7.2.1 Bus Timing
In user mode, the internal bus frequency is either the oscillator output (CGMXCLK) divided by four or the
divided PLL output (CGMPCLK) divided by four.
$FE04
Interrupt Status Register 1
(INT1)
Read: IF6 IF5 IF4 IF3 IF2 IF1 0 0
Write: RRRRRRRR
Reset:00000000
$FE05
Interrupt Status Register 2
(INT2)
Read: IF14 IF13 IF12 IF11 IF10 IF9 IF8 IF7
Write: RRRRRRRR
Reset: 00000000
$FE06
Interrupt Status Register 3
(INT3)
Read: 0 IF21 IF20 IF19 IF18 IF17 IF16 IF15
Write: RRRRRRRR
Reset: 00000000
= Unimplemented
Figure 7-2. SIM I/O Register Summary
÷ 2
BUS CLOCK
GENERATORS
SYSTEM INTEGRATION MODULE
MONITOR MODE
USER MODE
SIMOSCEN
OSCILLATOR (OSC) MODULE
OSC2
OSC1
PHASE-LOCKED LOOP (PLL)
CGMXCLK
CGMRCLK
IT12
CGMOUT
SIMDIV2
PTB0
TO TIM, ADC
STOP MODE CLOCK
TO REST
OF MCU
IT23
TO REST
OF MCU
ENABLE SIGNALS
FROM CONFIG2
ICLK
TO TBM
OSCCLK
CGMVCLK
TO PWM
SIM COUNTER