Datasheet

MC68HC908AP Family Data Sheet, Rev. 4

Freescale Semiconductor 97

Chapter 7

System Integration Module (SIM)

7.1 Introduction

This section describes the system integration module (SIM). Together with the CPU, the SIM controls all

MCU activities. A block diagram of the SIM is shown in Figure 7-1. Figure 7-2 is a summary of the SIM

input/output (I/O) registers. The SIM is a system state controller that coordinates CPU and exception

timing. The SIM is responsible for:

• Bus clock generation and control for CPU and peripherals:

– Stop/wait/reset/break entry and recovery

– Internal clock control

• Master reset control, including power-on reset (POR) and COP timeout

• Interrupt control:

– Acknowledge timing

– Arbitration control timing

– Vector address generation

• CPU enable/disable timing

• Modular architecture expandable to 128 interrupt sources

Table 7-1 shows the internal signal names used in this section.

Table 7-1. Signal Name Conventions

Signal Name Description

ICLK Internal oscillator clock

CGMXCLK Selected oscillator clock from oscillator module

CGMVCLK, CGMPCLK PLL output and the divided PLL output

CGMOUT

CGMPCLK-based or oscillator-based clock output from CGM module

(Bus clock = CGMOUT ÷ 2)

IAB Internal address bus

IDB Internal data bus

PORRST Signal from the power-on reset module to the SIM

IRST Internal reset signal

W Read/write signal