Datasheet

Clock Generator Module (CGM)
MC68HC908AP Family Data Sheet, Rev. 4
84 Freescale Semiconductor
1. Choose the desired bus frequency, f
BUSDES
, or the desired VCO frequency, f
VCLKDES
; and then
solve for the other.
The relationship between f
BUS
and f
VCLK
is governed by the equation:
where P is the power of two multiplier, and can be 0, 1, 2, or 3
2. Choose a practical PLL reference frequency, f
RCLK
, and the reference clock divider, R. Typically,
the reference is 32.768kHz and R = 1.
Frequency errors to the PLL are corrected at a rate of f
RCLK
/R. For stability and lock time reduction,
this rate must be as fast as possible. The VCO frequency must be an integer multiple of this rate.
The relationship between the VCO frequency, f
VCLK
, and the reference frequency, f
RCLK
,is
where N is the integer range multiplier, between 1 and 4095.
In cases where desired bus frequency has some tolerance, choose f
RCLK
to a value determined
either by other module requirements (such as modules which are clocked by CGMXCLK), cost
requirements, or ideally, as high as the specified range allows. See Chapter 22 Electrical
Specifications.
Choose the reference divider, R = 1.
When the tolerance on the bus frequency is tight, choose f
RCLK
to an integer divisor of f
BUSDES
,
and R = 1. If f
RCLK
cannot meet this requirement, use the following equation to solve for R with
practical choices of f
RCLK
, and choose the f
RCLK
that gives the lowest R.
3. Calculate N:
4. Calculate and verify the adequacy of the VCO and bus frequencies f
VCLK
and f
BUS
.
f
VCLK
2
P
f
CGMPCLK
× 2
P
4× f
BUS
×==
f
VCLK
2
P
N
R
----------- f
RCLK
()=
R round R
MAX
f
VCLKDES
f
RCLK
--------------------------
⎝⎠
⎜⎟
⎛⎞
integer
f
VCLKDES
f
RCLK
--------------------------
⎝⎠
⎜⎟
⎛⎞
–
⎩⎭
⎨⎬
⎧⎫
×=
N round
Rf
VCLKDES
×
f
RCLK
2
P
×
-------------------------------------
⎝⎠
⎜⎟
⎛⎞
=
f
BUS
f
VCLK
2
P
4×
-----------
=
f
VCLK
2
P
N
R
----------- f
RCLK
()=