Datasheet
Functional Description
MC68HC908AP Family Data Sheet, Rev. 4
Freescale Semiconductor 81
6.3.1 Oscillator Module
The oscillator module provides two clock outputs CGMXCLK and CGMRCLK to the CGM module.
CGMXCLK when selected, is driven to SIM module to generate the system bus clock. CGMRCLK is used
by the phase-lock-loop to provide a higher frequency system bus clock. The oscillator module also
provides the reference clock for the timebase module (TBM). See Chapter 5 Oscillator (OSC) for detailed
oscillator circuit description. See Chapter 10 Timebase Module (TBM) for detailed description on TBM.
6.3.2 Phase-Locked Loop Circuit (PLL)
The PLL is a frequency generator that can operate in either acquisition mode or tracking mode, depending
on the accuracy of the output frequency. The PLL can change between acquisition and tracking modes
either automatically or manually.
6.3.3 PLL Circuits
The PLL consists of these circuits:
• Voltage-controlled oscillator (VCO)
• Reference divider
• Frequency pre-scaler
• Modulo VCO frequency divider
Addr. Register Name Bit 7 654321Bit 0
$0036
PLL Control Register
(PTCL)
Read:
PLLIE
PLLF
PLLON BCS PRE1 PRE0 VPR1 VPR0
Write:
Reset:00100000
$0037
PLL Bandwidth Control
Register
(PBWC)
Read:
AUTO
LOCK
ACQ
0000
R
Write:
Reset:0000000
$0038
PLL Multiplier Select
Register High
(PMSH)
Read: 0000
MUL11 MUL10 MUL9 MUL8
Write:
Reset:00000000
$0039
PLL Multiplier Select
Register Low
(PMSL)
Read:
MUL7 MUL6 MUL5 MUL4 MUL3 MUL2 MUL1 MUL0
Write:
Reset:01000000
$003A
PLL VCO Range Select
Register
(PMRS)
Read:
VRS7 VRS6 VRS5 VRS4 VRS3 VRS2 VRS1 VRS0
Write:
Reset:01000000
$003B
PLL Reference Divider
Select Register
(PMDS)
Read: 0000
RDS3 RDS2 RDS1 RDS0
Write:
Reset:00000001
= Unimplemented R
= Reserved
NOTES:
1. When AUTO = 0, PLLIE is forced clear and is read-only.
2. When AUTO = 0, PLLF and LOCK read as clear.
3. When AUTO = 1,
ACQ is read-only.
4. When PLLON = 0 or VRS7:VRS0 = $0, BCS is forced clear and is read-only.
5. When PLLON = 1, the PLL programming register is read-only.
6. When BCS = 1, PLLON is forced set and is read-only.
Figure 6-2. CGM I/O Register Summary