Datasheet

Clock Generator Module (CGM)
MC68HC908AP Family Data Sheet, Rev. 4
80 Freescale Semiconductor
Figure 6-1. CGM Block Diagram
BCS
PHASE
DETECTOR
LOOP
FILTER
FREQUENCY
DIVIDER
VOLTAGE
CONTROLLED
OSCILLATOR
AUTOMATIC
MODE
CONTROL
LOCK
DETECTOR
CLOCK
CGMXCLK
CGMOUT
CGMVDV
INTERRUPT
CONTROL
CGMINT
CGMRDV
PLL ANALOG
÷ 2
CGMRCLK
SELECT
CIRCUIT
V
DDA
CGMXFC V
SSA
LOCK AUTO ACQ
VPR[1:0]
PLLIE PLLF
MUL[11:0]
REFERENCE
DIVIDER
VRS[7:0]
FREQUENCY
DIVIDER
PRE[1:0]
To ADC
PHASE-LOCKED LOOP (PLL)
A
B
1
S*
*WHEN S = 1,
CGMOUT = B
SIMDIV2
From SIM
To SIM
To SIM
RDS[3:0]
R
CGMPCLK
SIMOSCEN
OSCILLATOR (OSC) MODULE
OSC2
OSCSEL[1:0]
OSCCLK[1:0]
OSC1
From SIM
ICLK
CGMRCLK
INTERNAL OSCILLATOR
RC OSCILLATOR
CRYSTAL OSCILLATOR
MUX
See Chapter 5 Oscillator (OSC).
N
OSCCLK
To Timebase Module (TBM)
To SIM (and COP)
L
2
P
2
E
CGMVCLK