Datasheet

Central Processor Unit (CPU)

MC68HC908AP Family Data Sheet, Rev. 4

68 Freescale Semiconductor

A Accumulator n Any bit

C Carry/borrow bit opr Operand (one or two bytes)

CCR Condition code register PC Program counter

dd Direct address of operand PCH Program counter high byte

dd rr Direct address of operand and relative offset of branch instruction PCL Program counter low byte

DD Direct to direct addressing mode REL Relative addressing mode

DIR Direct addressing mode rel Relative program counter offset byte

DIX+ Direct to indexed with post increment addressing mode rr Relative program counter offset byte

ee ff High and low bytes of offset in indexed, 16-bit offset addressing SP1 Stack pointer, 8-bit offset addressing mode

EXT Extended addressing mode SP2 Stack pointer 16-bit offset addressing mode

ff Offset byte in indexed, 8-bit offset addressing SP Stack pointer

H Half-carry bit U Undeﬁned

H Index register high byte V Overﬂow bit

hh ll High and low bytes of operand address in extended addressing X Index register low byte

I Interrupt mask Z Zero bit

ii Immediate operand byte & Logical AND

IMD Immediate source to direct destination addressing mode | Logical OR

IMM Immediate addressing mode ⊕ Logical EXCLUSIVE OR

INH Inherent addressing mode ( ) Contents of

IX Indexed, no offset addressing mode –( ) Negation (two’s complement)

IX+ Indexed, no offset, post increment addressing mode # Immediate value

IX+D Indexed with post increment to direct addressing mode « Sign extend

IX1 Indexed, 8-bit offset addressing mode ← Loaded with

IX1+ Indexed, 8-bit offset, post increment addressing mode ? If

IX2 Indexed, 16-bit offset addressing mode : Concatenated with

M Memory location o Set or cleared

N Negative bit — Not affected

Table 4-1. Instruction Set Summary

Source

Form

Operation Description

Effect on

CCR

Address

Mode

Opcode

Operand

Cycles

VH I NZC