Datasheet

Opcode Map
MC68HC908AP Family Data Sheet, Rev. 4
Freescale Semiconductor 67
STX opr
STX opr
STX opr,X
STX opr,X
STX ,X
STX opr,SP
STX opr,SP
Store X in M M ← (X) 0 – – oo–
DIR
EXT
IX2
IX1
IX
SP1
SP2
BF
CF
DF
EF
FF
9EEF
9EDF
dd
hh ll
ee ff
ff
ff
ee ff
3
4
4
3
2
4
5
SUB #opr
SUB opr
SUB opr
SUB opr,X
SUB opr,X
SUB ,X
SUB opr,SP
SUB opr,SP
Subtract A ← (A) – (M) o ––ooo
IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2
A0
B0
C0
D0
E0
F0
9EE0
9ED0
ii
dd
hh ll
ee ff
ff
ff
ee ff
2
3
4
4
3
2
4
5
SWI Software Interrupt
PC ← (PC) + 1; Push (PCL)
SP ← (SP) – 1; Push (PCH)
SP ← (SP) – 1; Push (X)
SP ← (SP) – 1; Push (A)
SP ← (SP) – 1; Push (CCR)
SP ← (SP) – 1; I ← 1
PCH ← Interrupt Vector High Byte
PCL ← Interrupt Vector Low Byte
– – 1 – – – INH 83 9
TAP Transfer A to CCR CCR ← (A) ooooooINH 84 2
TAX Transfer A to X X ← (A) – – – – – – INH 97 1
TPA Transfer CCR to A A ← (CCR) – – – – – – INH 85 1
TST opr
TSTA
TSTX
TST opr,X
TST ,X
TST opr,SP
Test for Negative or Zero (A) – $00 or (X) – $00 or (M) – $00 0 – – oo–
DIR
INH
INH
IX1
IX
SP1
3D
4D
5D
6D
7D
9E6D
dd
ff
ff
3
1
1
3
2
4
TSX Transfer SP to H:X H:X ← (SP) + 1 – – – – – – INH 95 2
TXA Transfer X to A A ← (X) – – – – – – INH 9F 1
TXS Transfer H:X to SP (SP) ← (H:X) – 1 – – – – – – INH 94 2
WAIT Enable Interrupts; Wait for Interrupt
I ← 0; Inhibit CPU clocking until
interrupted
– – 0 – – – INH 8F 1
Table 4-1. Instruction Set Summary
Source
Form
Operation Description
Effect on
CCR
Address
Mode
Opcode
Operand
Cycles
VH I NZC