Datasheet

MC68HC908AP Family Data Sheet, Rev. 4
Freescale Semiconductor 49
Chapter 3
Configuration & Mask Option Registers (CONFIG & MOR)
3.1 Introduction
This section describes the configuration registers, CONFIG1 and CONFIG2; and the mask option
register, MOR.
The configuration registers enable or disable these options:
• Computer operating properly module (COP)
• COP timeout period (2
18
– 2
4
or 2
13
– 2
4
ICLK cycles)
• Low-voltage inhibit (LVI) on V
DD
• LVI on V
REG
• LVI module reset
• LVI module in stop mode
• STOP instruction
• Stop mode recovery time (32 ICLK or 4096 ICLK cycles)
• Oscillator (internal, RC, and crystal) during stop mode
• Serial communications interface clock source (CGMXCLK or f
BUS
)
The mask option register selects one of the following oscillator options:
• Internal oscillator
• RC oscillator
• Crystal oscillator
Addr. Register Name Bit 7 654321Bit 0
$001D
Configuration Register 2
(CONFIG2)
†
Read:
STOP_
ICLKDIS
STOP_
RCLKEN
STOP_
XCLKEN
OSCCLK1 OSCCLK0
00
SCIBDSRC
Write:
Reset: 00000000
$001F
Configuration Register 1
(CONFIG1)
†
Read:
COPRS LVISTOP LVIRSTD LVIPWRD
LVIREGD SSREC STOP COPD
Write:
Reset: 00000000
$FFCF
Mask-Option-Register
(MOR)
#
Read:
OSCSEL1 OSCSEL0 RRRRRR
Write:
Erased:11111111
† One-time writable register after each reset.
#
MOR is a non-volatile FLASH register; write by programming.
= Unimplemented R = Reserved
Figure 3-1. CONFIG and MOR Registers Summary