Datasheet

MC68HC908AP Family Data Sheet, Rev. 4
4 Freescale Semiconductor
Revision History
Date
Revision
Level
Description
Page
Number(s)
January 2007 4
15.7.2 ADC Clock Control Register — Changed “The ADC clock should
be set to between 500kHz and 2MHz” to “The ADC clock should be set
to between 500kHz and 1MHz”
254
August 2005 3
Table 22-4 . DC Electrical Characteristics (5V) — Updated V
OL
values.
299
Table 22-6 . Oscillator Specifications (5V) and Table 22-10 . Oscillator
Specifications (3V) — Corrected internal oscillator clock frequency,
f
ICLK
. Updated crystal oscillator component values C
L
, C
1
, C
2
, R
B
, and
R
S
.
301, 305
October 2003 2.5
Added MC68HC908AP16/AP8 information throughout. —
Section 10. Monitor ROM (MON) — Corrected RAM address to $60. 167
Section 24. Electrical Specifications — Added run and wait I
DD
data for
8MHz at 3V.
421
August 2003 2.4
Section 24. Electrical Specifications — Updated stop I
DD
data.
417, 421
July 2003 2.3
Removed MC68HC908AP16 references throughout. —
Table 1-2 . Pin Functions — Added footnote for V
REG
.
30
5.3 Configuration Register 1 (CONFIG1) — Clarified LVIPWRD and
LVIREGD bits.
67
Section 8. Clock Generator Module (CGM), 8.7.2 Stop Mode — Updated
BSC bit behavior.
125
10.5 ROM-Resident Routines — Corrected data size limits and control
byte size for EE_READ and EE_WRITE.
168–193
Figure 12-2 . Timebase Control Register (TBCR) — Corrected register
address.
207
Section 24. Electrical Specifications — Updated. 415
May 2003 2.2
Updated for f
NOM
= 125kHz and filter components
in CGM section.
101
Updated electricals. 415