Datasheet

Monitor ROM
MC68HC908AP Family Data Sheet, Rev. 4
Freescale Semiconductor 35
$0033
Timer 2 Channel 1 Status and
Control Register (T2SC1)
Read: CH1F
CH1IE
0
MS1A ELS1B ELS1A TOV1 CH1MAX
Write: 0
Reset: 00000000
$0034
Timer 2 Channel 1
Register High
(T2CH1H)
Read:
Bit 15 14 13 12 11 10 9 Bit 8
Write:
Reset: Indeterminate after reset
$0035
Timer 2 Channel 1
Register Low
(T2CH1L)
Read:
Bit 7654321Bit 0
Write:
Reset: Indeterminate after reset
$0036 PLL Control Register (PCTL)
Read:
PLLIE
PLLF
PLLON BCS PRE1 PRE0 VPR1 VPR0
Write:
Reset: 00100000
$0037
PLL Bandwidth Control Reg-
ister
(PBWC)
Read:
AUTO
LOCK
ACQ
0000
R
Write:
Reset: 00000000
$0038
PLL Multiplier Select
Register High
(PMSH)
Read:0000
MUL11 MUL10 MUL9 MUL8
Write:
Reset: 00000000
$0039
PLL Multiplier Select
Register Low
(PMSL)
Read:
MUL7 MUL6 MUL5 MUL4 MUL3 MUL2 MUL1 MUL0
Write:
Reset: 01000000
$003A
PLL VCO Range Select
Register
(PMRS)
Read:
VRS7 VRS6 VRS5 VRS4 VRS3 VRS2 VRS1 VRS0
Write:
Reset: 01000000
$003B
PLL Reference Divider
Select Register
(PMDS)
Read:0000
RDS3 RDS2 RDS1 RDS0
Write:
Reset: 00000001
$003C Unimplemented
Read:
Write:
Reset:
$003D Unimplemented
Read:
Write:
Reset:
$003E Unimplemented
Read:
Write:
Reset:
$003F Unimplemented
Read:
Write:
Reset:
Addr. Register Name Bit 7 654321Bit 0
U = Unaffected X = Indeterminate
= Unimplemented R = Reserved
Figure 2-2. Control, Status, and Data Registers (Sheet 5 of 9)