Datasheet

Electrical Specifications
MC68HC908AP Family Data Sheet, Rev. 4
304 Freescale Semiconductor
22.10 3V Control Timing
Pullup resistors
(10)
PTD[0:7]
RST,
IRQ1, IRQ2
R
PU1
R
PU2
21
21
27
27
39
39
kΩ
kΩ
Low-voltage inhibit, trip falling voltage1
(11)
V
TRIPF1
2.25 2.45 2.65 V
Low-voltage inhibit, trip rising voltage1
(10)
V
TRIPR1
2.35 2.55 2.75 V
Low-voltage inhibit, trip voltage2
(10)
V
TRIPF2
2.25 2.45 2.65 V
V
REG
(10), (12)
V
REG
2.25 2.50 2.75 V
1. V
DD
= 2.7 to 3.3 Vdc, V
SS
= 0 Vdc, T
A
= T
L
to T
H
, unless otherwise noted.
2. Typical values reflect average measurements at midpoint of voltage range, 25 °C only.
3. At V
DD
= 3V, an on-chip charge pump is activated for the V
REG
regulator, therefore some I
DD
values will appear higher
than the I
DD
values at V
DD
= 5V.
4. Run (operating) I
DD
measured using external 16MHz/32MHz clock to OSC1; all inputs 0.2 V from rail; no dc loads; less
than 100 pF on all outputs; C
L
= 20 pF on OSC2; all ports configured as inputs; OSC2 capacitance linearly affects run I
DD
;
measured with all modules enabled.
5. Wait I
DD
measured using external 16MHz/32MHz clock to OSC1; all inputs 0.2 V from rail; no dc loads; less than 100 pF
on all outputs. C
L
= 20 pF on OSC2; all ports configured as inputs; OSC2 capacitance linearly affects wait I
DD
.
6. STOP I
DD
measured with external 32.768kHz clock to OSC1; no port pins sourcing current.
7. STOP I
DD
measured with OSC1 grounded; no port pins sourcing current.
8. Maximum is highest voltage that POR is guaranteed. The rearm voltage is triggered by V
REG
.
9. If minimum V
DD
is not reached before the internal POR reset is released, RST must be driven low externally until minimum
V
DD
is reached.
10. R
PU1
and R
PU2
are measured at V
DD
= 5.0V
11. Values are not affected by operating V
DD
; they are the same for 3V and 5V.
12. Measured from V
DD
= V
TRIPF1
(Min) to 5.5 V.
Table 22-9. Control Timing (3V)
Characteristic
(1)
1. V
DD
= 2.7 to 3.3 Vdc, V
SS
= 0 Vdc; timing shown with respect to 20% V
DD
and 70% V
DD
, unless otherwise noted.
Symbol Min Max Unit
Internal operating frequency
(2)
2. Some modules may require a minimum frequency greater than dc for proper operation; see appropriate table for this in-
formation.
f
OP
— 8 MHz
RST input pulse width low
(3)
3. Minimum pulse width reset is guaranteed to be recognized. It is possible for a smaller pulse width to cause a reset.
t
IRL
750 — ns
Table 22-8. DC Electrical Characteristics (3V)
Characteristic
(1)
Symbol Min
Typ
(2)
Max Unit