Datasheet

MC68HC908AP Family Data Sheet, Rev. 4
Freescale Semiconductor 291
Chapter 21
Break Module (BRK)
21.1 Introduction
This section describes the break module. The break module can generate a break interrupt that stops
normal program flow at a defined address to enter a background program.
21.2 Features
Features of the break module include:
• Accessible input/output (I/O) registers during the break interrupt
• CPU-generated break interrupts
• Software-generated break interrupts
• COP disabling during break interrupts
21.3 Functional Description
When the internal address bus matches the value written in the break address registers, the break module
issues a breakpoint signal to the CPU. The CPU then loads the instruction register with a software
interrupt instruction (SWI) after completion of the current CPU instruction. The program counter vectors
to $FFFC and $FFFD ($FEFC and $FEFD in monitor mode).
Addr. Register Name Bit 7 654321Bit 0
$FE00
SIM Break Status Register
(SBSR)
Read:
RRRRRR
SBSW
R
Write:
Note
Reset:
0
$FE03
SIM Break Flag Control
Register
(SBFCR)
Read:
BCFE RRRRRRR
Write:
Reset:
0
$FE0C
Break Address
Register High
(BRKH)
Read:
Bit 15 14 13 12 11 10 9 Bit 8
Write:
Reset:
00000000
$FE0D
Break Address
Register Low
(BRKL)
Read:
Bit 7654321Bit 0
Write:
Reset:
00000000
$FE0E
Break Status and Control
Register
(BRKSCR)
Read:
BRKE BRKA
000000
Write:
Reset:
00000000
Note: Writing a logic 0 clears BW. = Unimplemented
R
= Reserved
Figure 21-1. Break Module I/O Register Summary