Datasheet

LVI Status Register
MC68HC908AP Family Data Sheet, Rev. 4
Freescale Semiconductor 289
20.3.4 Forced Reset Operation
In applications that require V
DD
to remain above the V
TRIPF1
level, enabling LVI resets allows the LVI
module to reset the MCU when V
DD
falls below the V
TRIPF1
level. In the CONFIG1 register, the LVIPWRD
and LVIRSTD bits must be at logic 0 to enable the LVI module and to enable LVI resets.
20.3.5 Voltage Hysteresis Protection
Once the LVI has triggered (by having V
DD
fall below V
TRIPF1
), the LVI will maintain a reset condition until
V
DD
rises above the rising trip point voltage, V
TRIPR1
. This prevents a condition in which the MCU is
continually entering and exiting reset if V
DD
is approximately equal to V
TRIPF1
. V
TRIPR1
is greater than
V
TRIPF1
by the hysteresis voltage, V
HYS
.
20.4 LVI Status Register
The LVI status register (LVISR) indicates if the V
DD
voltage was detected below V
TRIPF1
or V
REG
voltage
was detected below V
TRIPF2
.
LVIOUT — LVI Output Bit
This read-only flag becomes set when the V
DD
or V
REG
falls below their respective trip voltages. Reset
clears the LVIOUT bit.
20.5 LVI Interrupts
The LVI module does not generate interrupt requests.
Address: $FE0F
Bit 7654321Bit 0
Read: LVIOUT 0000000
Write:
Reset:00000000
= Unimplemented
Figure 20-3. LVI Status Register
Table 20-1. LVIOUT Bit Indication
V
DD
, V
REG
LVIOUT
V
DD
> V
TRIPR1
and
V
REG
> V
TRIPR2
0
V
DD
< V
TRIPF1
or
V
DD
< V
TRIPF2
1
V
TRIPF1
< V
DD
< V
TRIPR1
or
V
TRIPF2
< V
REG
< V
TRIPR2
Previous value