Datasheet

Low-Voltage Inhibit (LVI)
MC68HC908AP Family Data Sheet, Rev. 4
288 Freescale Semiconductor
an LVI reset occurs, the MCU remains in reset until V
DD
rises above V
TRIPR1
and V
REG
rises above
V
TRIPR2
, which causes the MCU to exit reset. The output of the comparator controls the state of the
LVIOUT flag in the LVI status register (LVISR).
An LVI reset also drives the
RST pin low to provide low-voltage protection to external peripheral devices.
Figure 20-2. LVI Module Block Diagram
20.3.1 Low V
DD
Detector
The low V
DD
detector circuit monitors the V
DD
voltage and forces a LVI reset when the V
DD
voltage falls
below the trip voltage, V
TRIPF1
. The V
DD
LVI circuit can be disabled by the setting the LVIPWRD bit in
CONFIG1 register.
20.3.2 Low V
REG
Detector
The low V
REG
detector circuit monitors the V
REG
voltage and forces a LVI reset when the V
REG
voltage
falls below the trip voltage, V
TRIPF2
. The V
REG
LVI circuit can be disabled by the setting the LVIREGD bit
in CONFIG1 register.
20.3.3 Polled LVI Operation
In applications that can operate at V
DD
levels below the V
TRIPF1
level, software can monitor V
DD
by polling
the LVIOUT bit. In the CONFIG1 register, the LVIPWRD bit must be at logic 0 to enable the LVI module,
and the LVIRSTD bit must be at logic 1 to disable LVI resets.
LOW V
DD
DETECTOR
LVIPWRD
STOP INSTRUCTION
LVI RESET
V
DD
> V
TRIPR1
= 0
V
DD
≤ V
TRIPF1
= 1
FROM CONFIG1
FROM CONFIG1
V
DD
FROM CONFIG1
TO LVISR
LVIOUT
LVISTOP
LVIRSTD
DETECTOR
LOW V
REG
LVIREGD
STOP INSTRUCTION
V
REG
≤ V
TRIPF2
= 1
V
REG
> V
TRIPR2
= 0
FROM CONFIG1
V
REG
FROM CONFIG1
LVISTOP