Datasheet

MC68HC908AP Family Data Sheet, Rev. 4
Freescale Semiconductor 287
Chapter 20
Low-Voltage Inhibit (LVI)
20.1 Introduction
This section describes the low-voltage inhibit (LVI) module. The LVI module monitors the voltage on the
V
DD
pin and V
REG
pin, and can force a reset when V
DD
voltage falls below V
TRIPF1
,orV
REG
voltage falls
below V
TRIPF2
.
NOTE
The V
REG
pin is the output of the internal voltage regulator and is
guaranteed to meet operating specification as long as V
DD
is within the
MCU operating voltage.
The LVI feature is intended to provide the safe shutdown of the
microcontroller and thus protection of related circuitry prior to any
application V
DD
voltage collapsing completely to an unsafe level. It is not
intended that users operate the microcontroller at lower than the specified
operating voltage, V
DD.
20.2 Features
Features of the LVI module include:
• Independent voltage monitoring circuits for V
DD
and V
REG
• Independent disable for V
DD
and V
REG
LVI circuits
• Programmable LVI reset
• Programmable stop mode operation
20.3 Functional Description
Figure 20-2 shows the structure of the LVI module. The LVI is enabled out of reset. The LVI module
contains independent bandgap reference circuit and comparator for monitoring the V
DD
voltage and the
V
REG
voltage. An LVI reset performs a MCU internal reset and drives the RST pin low to provide
low-voltage protection to external peripheral devices.
LVISTOP, LVIPWRD, LVIRSTD, and LVIREGD are in the CONFIG1 register. See Chapter 3
Configuration & Mask Option Registers (CONFIG & MOR) for details of the LVI configuration bits. Once
Addr. Register Name Bit 7 654321Bit 0
$FE0F
LVI Status Register
(LVISR)
Read: LVIOUT 0000000
Write:
Reset:00000000
= Unimplemented
Figure 20-1. LVI I/O Register Summary