Datasheet

COP Control Register
MC68HC908AP Family Data Sheet, Rev. 4
Freescale Semiconductor 285
19.3.8 COPRS (COP Rate Select)
The COPRS signal reflects the state of the COP rate select bit (COPRS) in the CONFIG1 register.
COPRS — COP Rate Select Bit
COPRS selects the COP time out period. Reset clears COPRS.
1 = COP time out period = 2
13
– 2
4
ICLK cycles
0 = COP time out period = 2
18
– 2
4
ICLK cycles
COPD — COP Disable Bit
COPD disables the COP module.
1 = COP module disabled
0 = COP module enabled
19.4 COP Control Register
The COP control register is located at address $FFFF and overlaps the reset vector. Writing any value to
$FFFF clears the COP counter and starts a new timeout period. Reading location $FFFF returns the low
byte of the reset vector.
19.5 Interrupts
The COP does not generate CPU interrupt requests.
19.6 Monitor Mode
When monitor mode is entered with V
TST
on the IRQ1 pin, the COP is disabled as long as V
TST
remains
on the
IRQ1 pin or the RST pin. When monitor mode is entered by having blank reset vectors and not
having V
TST
on the IRQ1 pin, the COP is automatically disabled until a POR occurs.
19.7 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power-consumption standby modes.
Address: $001F
Bit 7654321Bit 0
Read:
COPRS LVISTOP LVIRSTD LVIPWRD LVIREGD SSREC STOP COPD
Write:
Reset:00000000
Figure 19-2. Configuration Register 1 (CONFIG1)
Address: $FFFF
Bit 7654321Bit 0
Read: Low byte of reset vector
Write: Clear COP counter
Reset: Unaffected by reset
Figure 19-3. COP Control Register (COPCTL)