Datasheet

MC68HC908AP Family Data Sheet, Rev. 4
Freescale Semiconductor 283
Chapter 19
Computer Operating Properly (COP)
19.1 Introduction
The computer operating properly (COP) module contains a free-running counter that generates a reset if
allowed to overflow. The COP module helps software recover from runaway code. Prevent a COP reset
by clearing the COP counter periodically. The COP module can be disabled through the COPD bit in the
configuration register 1 (CONFIG1).
19.2 Functional Description
Figure 19-1 shows the structure of the COP module.
Figure 19-1. COP Block Diagram
The COP counter is a free-running 6-bit counter preceded by a 12-bit prescaler counter. If not cleared by
software, the COP counter overflows and generates an asynchronous reset after 2
18
–2
4
or 2
13
–2
4
ICLK cycles, depending on the state of the COP rate select bit, COPRS, in the CONFIG1 register. With
a2
13
–2
4
ICLK cycle overflow option, a 88-kHz ICLK gives a COP timeout period of ~93ms. Writing any
value to location $FFFF before an overflow occurs prevents a COP reset by clearing the COP counter
and stages 12 through 5 of the prescaler.
COPCTL WRITE
ICLK
RESET VECTOR FETCH
RESET CIRCUIT
RESET STATUS REGISTER
INTERNAL RESET SOURCES
12-BIT COP PRESCALER
CLEAR ALL STAGES
6-BIT COP COUNTER
COP DISABLE
RESET
COPCTL WRITE
CLEAR
COPEN (FROM SIM)
COP COUNTER
COP CLOCK
COP TIMEOUT
STOP INSTRUCTION
(COPD FROM CONFIG1)
COP RATE SEL
(COPRS FROM CONFIG1)
CLEAR STAGES 5–12