Datasheet

MC68HC908AP Family Data Sheet, Rev. 4
Freescale Semiconductor 271
Chapter 17
External Interrupt (IRQ)
17.1 Introduction
The external interrupt (IRQ) module provides two maskable interrupt inputs: IRQ1 and IRQ2.
17.2 Features
Features of the IRQ module include:
• A dedicated external interrupt pin,
IRQ1
• An external interrupt pin shared with a port pin, PTC0/
IRQ2
• Separate IRQ interrupt control bits for
IRQ1 and IRQ2
• Hysteresis buffers
• Programmable edge-only or edge and level interrupt sensitivity
• Automatic interrupt acknowledge
• Internal pullup resistor, with disable option on
IRQ2
NOTE
References to either IRQ1 or IRQ2 may be made in the following text by
omitting the IRQ number. For example, IRQF may refer generically to
IRQ1F and IRQ2F, and IMASK may refer to IMASK1 and IMASK2.
17.3 Functional Description
A logic 0 applied to the external interrupt pin can latch a CPU interrupt request. Figure 17-2 and
Figure 17-3 shows the structure of the IRQ module.
Interrupt signals on the
IRQ pin are latched into the IRQ latch. An interrupt latch remains set until one of
the following actions occurs:
• Vector fetch — A vector fetch automatically generates an interrupt acknowledge signal that clears
the latch that caused the vector fetch.
Addr. Register Name Bit 7 654321Bit 0
$001C
IRQ2 Status and Control
Register
(INTSCR2)
Read: 0
PUC0ENB
0 0 IRQ2F 0
IMASK2 MODE2
Write:
ACK2
Reset:00000000
$001E
IRQ1 Status and Control
Register
(INTSCR1)
Read: 0000IRQ1F 0
IMASK1 MODE1
Write: ACK1
Reset:00000000
= Unimplemented
Figure 17-1. External Interrupt I/O Register Summary