Datasheet

Input/Output (I/O) Ports
MC68HC908AP Family Data Sheet, Rev. 4
268 Freescale Semiconductor
PTD[7:0] — Port D Data Bits
These read/write bits are software programmable. Data direction of each port D pin is under the control
of the corresponding bit in data direction register D. Reset has no effect on port D data.
KBI7–KBI0 — Keyboard Interrupt Inputs
The keyboard interrupt enable bits, KBIE[7:0], in the keyboard interrupt enable register (KBIER),
enable the port D pins as external interrupt pins. See Chapter 18 Keyboard Interrupt Module (KBI).
16.5.2 Data Direction Register D (DDRD)
Data direction register D determines whether each port D pin is an input or an output. Writing a logic 1 to
a DDRD bit enables the output buffer for the corresponding port D pin; a logic 0 disables the output buffer.
DDRD[7:0] — Data Direction Register D Bits
These read/write bits control port D data direction. Reset clears DDRD[7:0], configuring all port D pins
as inputs.
1 = Corresponding port D pin configured as output
0 = Corresponding port D pin configured as input
NOTE
Avoid glitches on port D pins by writing to the port D data register before
changing data direction register D bits from 0 to 1.
Figure 16-14 shows the port D I/O logic.
Figure 16-14. Port D I/O Circuit
When bit DDRDx is a logic 1, reading address $0003 reads the PTDx data latch. When bit DDRDx is a
logic 0, reading address $0003 reads the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit.
Address: $0007
Bit 7654321Bit 0
Read:
DDRD7 DDRD6 DDRD5 DDRD4 DDRD3 DDRD2 DDRD1 DDRD0
Write:
Reset:00000000
Figure 16-13. Data Direction Register D (DDRD)
READ DDRD ($0007)
WRITE DDRD ($0007)
RESET
WRITE PTD ($0003)
READ PTD ($0003)
PTDx
#
DDRDx
PTDx
INTERNAL DATA BUS
KBIEx
# PTD7–PTD0 have schmitt trigger inputs.