Datasheet

I/O Registers
MC68HC908AP Family Data Sheet, Rev. 4
Freescale Semiconductor 257
15.7.4 ADC Auto-Scan Mode Data Registers (ADRL1–ADRL3)
The ADC data registers 1 to 3 (ADRL1–ADRL3), are 8-bit registers for conversion results in 8-bit
truncated mode, for channels ADC1 to ADC3, when the ADC is operating in auto-scan mode
(MODE[1:0] = 00).
15.7.5 ADC Auto-Scan Control Register (ADASCR)
The ADC auto-scan control register (ADASCR) enables and controls the ADC auto-scan function.
AUTO[1:0] — Auto-Scan Mode Channel Select Bits
AUTO1 and AUTO0 form a 2-bit field which is used to define the number of auto-scan channels used
when in auto-scan mode. Reset clears these bits.
Addr. Register Name Bit 7 654321Bit 0
$0059
ADC Data Register High 0
(ADRH0)
Read:
AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2
Write: RRRRRRRR
Reset:00000000
$005A
ADC Data Register Low 0
(ADRL0)
Read: AD1 AD0 000000
Write: RRRRRRRR
Reset:00000000
Figure 15-8 ADRH0 and ADRL0 in Left Justified Sign Data Mode
Address: ADRL1, $005B; ADRL2, $005C; and ADRL3, $005D
Read: AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2
Write: RRRRRRRR
Reset:00000000
R = Reserved
Figure 15-9. ADC Data Register Low 1 to 3 (ADRL1–ADRL3)
Address: $005E
Read: 00000
AUTO1 AUTO0 ASCAN
Write:
Reset:00000000
= Unimplemented R = Reserved
Figure 15-10. ADC Scan Control Register (ADASCR)
Table 15-4. Auto-scan Mode Channel Select
AUTO1 AUTO0 Auto-Scan Channels
0 0 ADC0 only
0 1 ADC0 to ADC1
1 0 ADC0 to ADC2
1 1 ADC0 to ADC3