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ManualsBrandsNXP SEMICONDUCTORS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller QFP 44 (10x10) 8-Bit 8 MHz I/O number 32
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Analog-to-Digital Converter (ADC)
MC68HC908AP Family Data Sheet, Rev. 4
256 Freescale Semiconductor
In right justified mode the ADRH0 holds the two MSBs, and the ADRL0 holds the eight least significant
bits (LSBs), of the 10-bit result. ADRH0 and ADRL0 are updated each time a single channel ADC
conversion completes. Reading ADRH0 latches the contents of ADRL0. Until ADRL0 is read all
subsequent ADC results will be lost. (See Figure 15-6 . ADRH0 and ADRL0 in Right Justified Mode.)
In left justified mode the ADRH0 holds the eight most significant bits (MSBs), and the ADRL0 holds the
two least significant bits (LSBs), of the 10-bit result. The ADRH0 and ADRL0 are updated each time a
single channel ADC conversion completes. Reading ADRH0 latches the contents of ADRL0. Until ADRL0
is read all subsequent ADC results will be lost. (See Figure 15-7 . ADRH0 and ADRL0 in Left Justified
Mode.)
In left justified sign mode the ADRH0 holds the eight MSBs with the MSB complemented, and the ADRL0
holds the two least significant bits (LSBs), of the 10-bit result. The ADRH0 and ADRL0 are updated each
time a single channel ADC conversion completes. Reading ADRH0 latches the contents of ADRL0. Until
ADRL0 is read all subsequent ADC results will be lost. (See Figure 15-8 ADRH0 and ADRL0 in Left
Justified Sign Data Mode.)
Addr. Register Name Bit 7 654321Bit 0
$0059
ADC Data Register High 0
(ADRH0)
Read: 00000000
Write: RRRRRRRR
Reset:00000000
$005A
ADC Data Register Low 0
(ADRL0)
Read: AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2
Write: RRRRRRRR
Reset:00000000
Figure 15-5. ADRH0 and ADRL0 in 8-Bit Truncated Mode
Addr. Register Name Bit 7 654321Bit 0
$0059
ADC Data Register High 0
(ADRH0)
Read: 000000AD9AD8
Write: RRRRRRRR
Reset:00000000
$005A
ADC Data Register Low 0
(ADRL0)
Read: AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0
Write: RRRRRRRR
Reset:00000000
Figure 15-6. ADRH0 and ADRL0 in Right Justified Mode
Addr. Register Name Bit 7 654321Bit 0
$0059
ADC Data Register High 0
(ADRH0)
Read: AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2
Write: RRRRRRRR
Reset:00000000
$005A
ADC Data Register Low 0
(ADRL0)
Read: AD1 AD0 000000
Write: RRRRRRRR
Reset:00000000
Figure 15-7. ADRH0 and ADRL0 in Left Justified Mode