Datasheet

Analog-to-Digital Converter (ADC)
MC68HC908AP Family Data Sheet, Rev. 4
254 Freescale Semiconductor
15.7.2 ADC Clock Control Register
The ADC clock control register (ADICLK) selects the clock frequency for the ADC.
ADIV[2:0] — ADC Clock Prescaler Bits
ADIV2, ADIV1, and ADIV0 form a 3-bit field which selects the divide ratio used by the ADC to generate
the internal ADC clock.
Table 15-2 shows the available clock configurations. The ADC clock should be set to between 500 kHz
and 1MHz.
Table 15-1. MUX Channel Select
ADCH4 ADCH3 ADCH2 ADCH1 ADCH0 ADC Channel Input Select
00000 ADC0 PTA0
00001 ADC1 PTA1
00010 ADC2 PTA2
00011 ADC3 PTA3
00100 ADC4 PTA4
00101 ADC5 PTA5
00110 ADC6 PTA6
00111 ADC7 PTA7
0
↓
1
1
↓
1
0
↓
1
0
↓
0
0
↓
0
ADC8
↓
ADC28
Reserved
11
1 0 1 ADC29
V
REFH
(see Note 2)
11
1 1 0 ADC30
V
REFL
(see Note 2)
11
1 1 1 ADC powered-off —
NOTES:
1. If any unused channels are selected, the resulting ADC conversion will be unknown.
2. The voltage levels supplied from internal reference nodes as specified in the table are used to verify the operation of
the ADC converter both in production test and for user applications.
Address: $0058
Read:
ADIV2 ADIV1 ADIV0 ADICLK MODE1 MODE0
00
Write:
R
Reset:00000100
= Unimplemented R = Reserved
Figure 15-4. ADC Clock Control Register (ADICLK)