Datasheet

Functional Description
MC68HC908AP Family Data Sheet, Rev. 4
Freescale Semiconductor 249
Figure 15-2. ADC Block Diagram
15.3.3 Conversion Time
Conversion starts after a write to the ADSCR. One conversion will take between 16 and 17 ADC clock
cycles, therefore:
ADC DATA REGISTERS
INTERNAL
DATA BUS
READ DDRAx
WRITE DDRAx
RESET
WRITE PTAx
READ PTAx
PTAx/ADCx
DDRAx
PTAx
INTERRUPT
LOGIC
CHANNEL
SELECT
10-BIT ADC
CLOCK
GENERATOR
CONVERSION
COMPLETE
ADC
(V
ADIN
)
ADCICLK
CGMXCLK
BUS CLOCK
ASCAN
DISABLE
DISABLE
(8 CHANNELS)
ADIV[2:0] ADICLK
VOLTAGE IN
VREFL
VREFH
ADCH[4:0]
ADC0–ADC7
MUX
2-BIT UP-COUNTER
COCOAIEN
ADRH0
ADRL1
ADRL0
ADRL2
ADRL3
AUTO[1:0]
16 to17 ADC cycles
Conversion time =
ADC frequency
Number of bus cycles = conversion time × bus frequency