Datasheet

Multi-Master IIC Bus Protocol
MC68HC908AP Family Data Sheet, Rev. 4
Freescale Semiconductor 231
14.5 Multi-Master IIC Bus Protocol
Normally a standard communication is composed of four parts:
1. START signal,
2. slave address transmission,
3. data transfer, and
4. STOP signal.
These are described briefly in the following sections and illustrated in Figure 14-2.
Figure 14-2. Multi-Master IIC Bus Transmission Signal Diagram
14.5.1 START Signal
When the bus is free, (i.e. no master device is engaging the bus — both SCL and SDA lines are at logic
high) a master may initiate communication by sending a START signal. As shown in Figure 14-2, a
START signal is defined as a high to low transition of SDA while SCL is high. This signal denotes the
beginning of a new data transfer (each data transfer may contain several bytes of data) and wakes up all
slaves.
14.5.2 Slave Address Transmission
The first byte transferred immediately after the START signal is the slave address transmitted by the
master. This is a 7-bit calling address followed by a R/W-bit. The R/W-bit dictates to the slave the desired
direction of the data transfer. A logic 0 indicates that the master wishes to transmit data to the slave; a
logic 1 indicates that the master wishes to receive data from the slave.
101 00011 1 01 10011
101 00011 1 01 10011
SCL
SDA
SCL
SDA
MSB LSB MSB LSB
MSB LSB MSB LSB
START STOP
Repeated
START STOP
9th clock pulse 9th clock pulse
ACK No ACK
signal signal
signalsignal
signal
ACK No ACK
START
Data must be stable
when SCL is HIGH