Datasheet

Multi-Master IIC Interface (MMIIC)
MC68HC908AP Family Data Sheet, Rev. 4
230 Freescale Semiconductor
14.3 I/O Pins
The MMIIC module uses two I/O pins, shared with standard port I/O pins. The full name of the MMIIC I/O
pins are listed in Table 14-1. The generic pin name appear in the text that follows.
The SDA and SDL pins are open-drain. When configured as general purpose output pins (PTB0 and
PTB1), pullup resistors must be connected to these pins.
14.4 Multi-Master IIC System Configuration
The multi-master IIC system uses a serial data line SDA and a serial clock line SCL for data transfer. All
devices connected to it must have open collector (drain) outputs and the logical-AND function is
performed on both lines by two pull-up resistors.
Table 14-1. Pin Name Conventions
MMIIC Generic Pin Names: Full MCU Pin Names: Pin Selected for MMIIC Function By:
SDA PTB0/SDA
MMEN bit in MMCR1 ($0049)
SCL PTB1/SCL
Addr. Register Name Bit 7 654321Bit 0
$0048
MMIIC Address Register
(MMADR)
Read:
MMAD7 MMAD6 MMAD5 MMAD4 MMAD3 MMAD2 MMAD1 MMEXTAD
Write:
Reset:10100000
$0049
MMIIC Control Register 1
(MMCR1)
Read:
MMEN MMIEN
00
MMTXAK REPSEN
MMCRCBYTE
0
Write: MMCLRBB
Reset:00000000
$004A
MMIIC Control Register 2
(MMCR2)
Read: MMALIF MMNAKIF MMBB
MMAST MMRW
00
MMCRCEF
Write: 0 0
Reset:0000000Unaffected
$004B
MMIIC Status Register
(MMSR)
Read: MMRXIF MMTXIF MMATCH MMSRW MMRXAK MMCRCBF MMTXBE MMRXBF
Write: 0 0
Reset:00001010
$004C
MMIIC Data Transmit
Register
(MMDTR)
Read:
MMTD7 MMTD6 MMTD5 MMTD4 MMTD3 MMTD2 MMTD1 MMTD0
Write:
Reset:00000000
$004D
MMIIC Data Receive
Register
(MDDRR)
Read: MMRD7 MMRD6 MMRD5 MMRD4 MMRD3 MMRD2 MMRD1 MMRD0
Write:
Reset:00000000
$004E
MMIIC CRC Data Register
(MMCRDR)
Read: MMCRCD7 MMCRCD6 MMCRCD5 MMCRCD4 MMCRCD3 MMCRCD2 MMCRCD1 MMCRCD0
Write:
Reset:00000000
$004F
MMIIC Frequency Divider
Register
(MMFDR)
Read: 00000
MMBR2 MMBR1 MMBR0
Write:
Reset:00000100
= Unimplemented
Figure 14-1. MMIIC I/O Register Summary