Datasheet

SCI Functional Description
MC68HC908AP Family Data Sheet, Rev. 4
Freescale Semiconductor 187
Figure 12-7. SCI Transmitter
12.5.2.2 Character Transmission
During an SCI transmission, the transmit shift register shifts a character out to the TxD pin. The IRSCI
data register (IRSCDR) is the write-only buffer between the internal data bus and the transmit shift
register. To initiate an SCI transmission:
1. Enable the SCI by writing a logic 1 to the enable SCI bit (ENSCI) in IRSCI control register 1
(IRSCC1).
2. Enable the transmitter by writing a logic 1 to the transmitter enable bit (TE) in IRSCI control register
2 (IRSCC2).
3. Clear the SCI transmitter empty bit by first reading IRSCI status register 1 (IRSCS1) and then
writing to the IRSCDR.
4. Repeat step 3 for each subsequent transmission.
At the start of a transmission, transmitter control logic automatically loads the transmit shift register with
a preamble of logic 1s. After the preamble shifts out, control logic transfers the IRSCDR data into the
transmit shift register. A logic 0 start bit automatically goes into the least significant bit position of the
transmit shift register. A logic 1 stop bit goes into the most significant bit position.
DMATE
SCTE
PEN
PTY
H876543210L
11-BIT
TRANSMIT
STOP START
T8
DMATE
SCTE
SCTIE
TCIE
SBK
TC
PARITY
GENERATION
MSB
SCI DATA REGISTER
LOAD FROM IRSCDR SHIFT ENABLE
PREAMBLE
ALL 1s
BREAK
ALL 0s
TRANSMITTER
CONTROL LOGIC
SHIFT REGISTER
DMATE
TC
SCTIE
TCIE
SCTE
TRANSMITTER CPU INTERRUPT REQUEST
TRANSMITTER DMA SERVICE REQUEST
M
ENSCI
LOOPS
TE
INTERNAL BUS
PRE-
SCALER
SCP1
SCP0
SCR2
SCR1
SCR0
BAUD
DIVIDER
÷ 16
SCTIE
SCI_TxD
CGMXCLK
BUS CLOCK
A
B
SL
X
SL = 0 => X = A
SL = 1 => X = B
CKS