Datasheet

MC68HC908AP Family Data Sheet, Rev. 4
118 Freescale Semiconductor Monitor ROM (MON)
Table 8-1. Monitor Mode Signal Requirements and Options
IRQ1 RST
Address
$FFFE/
$FFFF
PTA2 PTA1
PTA0
(1)
1. PTA0 = 1 if serial communication; PTA0 = 0 if parallel communication
PTB0
External
Clock
(2)
2. External clock is derived by a 32.768kHz crystal or a 4.9152/9.8304MHz off-chip oscillator.
Bus
Frequency
PLL COP
Baud
Rate
Comment
XGNDX XXXX X 0 XDisabled 0
No operation until
reset goes high
V
TST
(3)
3. Monitor mode entry by IRQ1= V
TST
, a 4.9152/9.8304 MHz off-chip oscillator must be used. The MCU internal crystal oscillator circuit is by-
passed.
V
DD
or
V
TST
X 0110
4.9152
MHz
2.4576
MHz
OFF Disabled 9600
PTA1 and PTA2
voltages only
required if
IRQ1 = V
TST
;
PTB0 determines
frequency divider
V
TST
(3)
V
DD
or
V
TST
X 0111
9.8304
MHz
2.4576
MHz
OFF Disabled 9600
PTA1 and PTA2
voltages only
required if
IRQ1 = V
TST
;
PTB0 determines
frequency divider
V
DD
V
DD
Blank
"$FFFF"
XX1X
9.8304
MHz
2.4576
MHz
OFF Disabled 9600
External frequency
always divided by 4
GND
V
DD
Blank
"$FFFF"
XX1X
32.768
kHz
2.4576
MHz
ON Disabled 9600
PLL enabled
(BCS set)
in monitor mode
V
DD
or
GND
V
TST
Blank
"$FFFF"
XXXX X — OFFEnabled —
Enters user
mode — will
encounter an illegal
address reset
V
DD
or
GND
V
DD
or
V
TST
Not Blank XXXX X — OFFEnabled — Enters user mode