Datasheet

Monitor ROM (MON)
MC68HC908AP Family Data Sheet, Rev. 4
116 Freescale Semiconductor
Figure 8-1. Monitor Mode Circuit
NOTES:
1. Monitor mode entry method:
SW2: Position C — High voltage entry (V
TST
); must use external OSC
Bus clock depends on SW1 (note 2).
SW2: Position D — Reset vector must be blank ($FFFE:$FFFF = $FF)
Bus clock = 1.2288MHz.
2. Affects high voltage entry to monitor mode only (SW2 at position C):
SW1: Position A — Bus clock = OSC1 4
SW1: Position B — Bus clock = OSC1 2
5. See Table 22-4 for V
TST
voltage level requirements.
1M
HC908AP
RST
IRQ1
OSC1
OSC2
V
SS
PTA0
6–30 pF
6–30 pF
0.1 µF
4.9152MHz
PTA1
V
DD
0.1 µF
V
DD
PTA2
10k
PTB0
V
DD
10k
10 k
SW1
A
B
V
REG
(SEE NOTE 2)
C
D
XTAL CIRCUIT
16
15
2
6
V
DD
MAX232
V+
V–
V
DD
10 k
C1+
C1–
5
4
C2+
C2–
+
3
1
1 µF
+
+
+
8
7
DB9
2
3
5
10
9
+
1
2
3
4
5
6
74HC125
74HC125
1k
V
TST
V
CC
GND
1 µF
1 µF
1 µF
1 µF
8.5 V
10 k
CONNECT TO OSC1, WITH OSC2 UNCONNECTED.
MUST BE USED IF SW2 IS AT POSITION C.
OSC1
(SEE NOTE 1)
SW2
10k
0.033 µF
0.01 µF
CGMXFC
V
DDA
V
REFL
V
SSA
EXT OSC
4.9152MHz/9.8304MHz
(50% DUTY)
V
REFH
V
REG
10k
V
DD
V
DD