Datasheet

Configuration Register (CONFIG)
MC68HC908AB32 — Rev. 1.1 Technical Data
Freescale Semiconductor Configuration Register (CONFIG)
87
LVIPWRD — LVI Power Disable Bit
LVIPWRD disables the LVI module. (See Section 21. Low-Voltage
Inhibit (LVI).)
1 = LVI module power disabled
0 = LVI module power enabled
SSREC — Short Stop Recovery Bit
SSREC enables the CPU to exit stop mode with a delay of 32
CGMXCLK cycles instead of a 4096 CGMXCLK cycle delay.
1 = STOP mode recovery after 32 CGMXCLK cycles
0 = STOP mode recovery after 4096 CGMXCLK cycles
NOTE: If using an external crystal oscillator, do not set the SSREC bit.
COPRS — COP Rate Select Bit
COPRS selects the COP timeout period. Reset clears COPRS. (See
Section 20. Computer Operating Properly (COP).)
1 = COP timeout period is 2
18
– 2
4
CGMXCLK cycles
0 = COP timeout period is 2
13
– 2
4
CGMXCLK cycles
STOP — STOP Instruction Enable Bit
STOP enables the STOP instruction.
1 = STOP instruction enabled
0 = STOP instruction treated as illegal opcode
COPD — COP Disable Bit
COPD disables the COP module. (See Section 20. Computer
Operating Properly (COP).)
1 = COP module disabled
0 = COP module enabled
Extra care should be exercised when using this emulation part for
development of code to be run in ROM AB, AS or AZ parts that the
options selected by setting the CONFIG1 register match exactly the
options selected on any ROM code request submitted. The
enable/disable logic is not necessarily identical in all parts of the
AB, AS, and AZ families. If in doubt, check with your local field
applications representative.