Datasheet

Computer Operating Properly (COP)
Technical Data MC68HC908AB32 — Rev. 1.1
356 Computer Operating Properly (COP) Freescale Semiconductor
20.4.5 Internal Reset
An internal reset clears the COP prescaler and the COP counter.
20.4.6 Reset Vector Fetch
A reset vector fetch occurs when the vector address appears on the data
bus. A reset vector fetch clears the COP prescaler.
20.4.7 COPD (COP Disable)
The COPD signal reflects the state of the COP disable bit (COPD) in the
configuration register 1. (See Figure 20-2.)
20.4.8 COPRS (COP Rate Select)
The COPRS signal reflects the state of the COP rate select bit (COPRS)
in the configuration register 1. (See Figure 20-2.)
COPRS — COP Rate Select Bit
COPRS selects the COP timeout period. Reset clears COPRS.
1 = COP timeout period is 2
18
– 2
4
CGMXCLK cycles
0 = COP timeout period is 2
13
– 2
4
CGMXCLK cycles
COPD — COP Disable Bit
COPD disables the COP module.
1 = COP module disabled
0 = COP module enabled
Address: $001F
Bit 7654321Bit 0
Read:
LVISTOP R LVIRSTD LVIPWRD SSREC COPRS STOP COPD
Write:
Reset:00000000
R=Reserved
Figure 20-2. Configuration Register 1 (CONFIG1)