Datasheet

Computer Operating Properly (COP)
MC68HC908AB32 — Rev. 1.1 Technical Data
Freescale Semiconductor Computer Operating Properly (COP)
355
A COP reset pulls the RST pin low for 32 CGMXCLK cycles and sets the
COP bit in the SIM reset status register (SRSR).
In monitor mode, the COP is disabled if the RST pin or the IRQ is held
at V
TST
During the break state, V
TST
on the RST pin disables the COP.
NOTE: Place COP clearing instructions in the main program and not in an
interrupt subroutine. Such an interrupt subroutine could keep the COP
from generating a reset even while the main program is not working
properly.
20.4 I/O Signals
The following paragraphs describe the signals shown in Figure 20-1.
20.4.1 CGMXCLK
CGMXCLK is the crystal oscillator output signal. CGMXCLK frequency
is equal to the crystal frequency.
20.4.2 STOP Instruction
The STOP instruction clears the COP prescaler.
20.4.3 COPCTL Write
Writing any value to the COP control register (COPCTL) (see 20.5 COP
Control Register) clears the COP counter and clears bits 12 through 5
of the prescaler. Reading the COP control register returns the low byte
of the reset vector.
20.4.4 Power-On Reset
The power-on reset (POR) circuit clears the COP prescaler 4096
CGMXCLK cycles after power-up.