Datasheet
Table Of Contents
- List of Sections
- Table of Contents
- List of Figures
- List of Tables
- Section 1. General Description
- 1.1 Contents
- 1.2 Introduction
- 1.3 Features
- 1.4 MCU Block Diagram
- 1.5 Pin Assignments
- 1.6 Pin Functions
- 1.6.1 Power Supply Pins (Vdd and Vss)
- 1.6.2 Oscillator Pins (OSC1 and OSC2)
- 1.6.3 External Reset Pin (RST)
- 1.6.4 External Interrupt Pin (IRQ)
- 1.6.5 Analog Power Supply Pin (VDDA)
- 1.6.6 Analog Ground Pin (VSSA)
- 1.6.7 Analog Ground Pin (AVSS/VREFL)
- 1.6.8 ADC Voltage Reference Pin (VREFH)
- 1.6.9 Analog Supply Pin (VDDAREF)
- 1.6.10 External Filter Capacitor Pin (CGMXFC)
- 1.6.11 Port A Input/Output (I/O) Pins (PTA7-PTA0)
- 1.6.12 Port B I/O Pins (PTB7/ATD7-PTB0/ATD0)
- 1.6.13 Port C I/O Pins (PTC5-PTC0)
- 1.6.14 Port D I/O Pins (PTD7-PTD0)
- 1.6.15 Port E I/O Pins (PTE7/SPSCK-PTE0/TxD)
- 1.6.16 Port F I/O Pins (PTF7-PTF0/TACH2)
- 1.6.17 Port G I/O Pins (PTG2/KBD2-PTG0/KBD0)
- 1.6.18 Port H I/O Pins (PTH1/KBD4-PTH0/KBD3)
- 1.7 I/O Pin Summary
- 1.8 Signal Name Conventions
- 1.9 Clock Source Summary
- Section 2. Memory Map
- Section 3. Random-Access Memory (RAM)
- Section 4. FLASH Memory
- Section 5. EEPROM
- Section 6. Configuration Register (CONFIG)
- Section 7. Central Processor Unit (CPU)
- Section 8. System Integration Module (SIM)
- Section 9. Clock Generator Module (CGM)
- 9.1 Contents
- 9.2 Introduction
- 9.3 Features
- 9.4 Functional Description
- 9.5 I/O Signals
- 9.5.1 Crystal Amplifier Input Pin (OSC1)
- 9.5.2 Crystal Amplifier Output Pin (OSC2)
- 9.5.3 External Filter Capacitor Pin (CGMXFC)
- 9.5.4 PLL Analog Power Pin (VDDA)
- 9.5.5 Oscillator Enable Signal (SIMOSCEN)
- 9.5.6 Crystal Output Frequency Signal (CGMXCLK)
- 9.5.7 CGM Base Clock Output (CGMOUT)
- 9.5.8 CGM CPU Interrupt (CGMINT)
- 9.6 CGM Registers
- 9.7 Interrupts
- 9.8 Low-Power Modes
- 9.9 CGM During Break Interrupts
- 9.10 Acquisition/Lock Time Specifications
- Section 10. Monitor ROM (MON)
- Section 11. Timer Interface Module A (TIMA)
- Section 12. Timer Interface Module B (TIMB)
- Section 13. Programmable Interrupt Timer (PIT)
- Section 14. Analog-to-Digital Converter (ADC)
- Section 15. Serial Communications Interface Module (SCI)
- Section 16. Serial Peripheral Interface Module (SPI)
- 16.1 Contents
- 16.2 Introduction
- 16.3 Features
- 16.4 Pin Name Conventions and I/O Register Addresses
- 16.5 Functional Description
- 16.6 Transmission Formats
- 16.7 Queuing Transmission Data
- 16.8 Error Conditions
- 16.9 Interrupts
- 16.10 Resetting the SPI
- 16.11 Low-Power Modes
- 16.12 SPI During Break Interrupts
- 16.13 I/O Signals
- 16.14 I/O Registers
- Section 17. Input/Output (I/O) Ports
- Section 18. External Interrupt (IRQ)
- Section 19. Keyboard Interrupt Module (KBI)
- Section 20. Computer Operating Properly (COP)
- Section 21. Low-Voltage Inhibit (LVI)
- Section 22. Break Module (BRK)
- Section 23. Electrical Specifications
- 23.1 Contents
- 23.2 Introduction
- 23.3 Absolute Maximum Ratings
- 23.4 Functional Operating Range
- 23.5 Thermal Characteristics
- 23.6 5.0-V DC Electrical Characteristics
- 23.7 EEPROM and Memory Characteristics
- 23.8 5.0-V Control Timing
- 23.9 Timer Interface Module Characteristics
- 23.10 ADC Characteristics
- 23.11 SPI Characteristics
- 23.12 Clock Generation Module Characteristics
- 23.13 FLASH Memory Characteristics
- Section 24. Mechanical Specifications
- Section 25. Ordering Information
Input/Output (I/O) Ports
Technical Data MC68HC908AB32 — Rev. 1.1
326 Input/Output (I/O) Ports Freescale Semiconductor
17.7 Port E
Port E is an 8-bit special function port that shares two of its pins with the
timer interface module (TIMA), two of its pins with the serial
communications interface module (SCI) and four of its pins with the
serial peripheral interface module (SPI).
17.7.1 Port E Data Register (PTE)
The port E data register contains a data latch for each of the eight port E
pins.
PTE[7:0] — Port E Data Bits
These read/write bits are software programmable. Data direction of
each port E pin is under the control of the corresponding bit in data
direction register E. Reset has no effect on port E data.
SPSCK — SPI Serial Clock
The PTE7/SPSCK pin is the serial clock input of a SPI slave module
and serial clock output of a SPI master modules. When the SPE bit is
clear, the PTE7/SPSCK pin is available for general-purpose I/O. See
16.14.1 SPI Control Register.
MOSI — Master Out/Slave In
The PTE6/MOSI pin is the master out/slave in terminal of the SPI
module. When the SPE bit is clear, the PTE6/MOSI pin is available for
general-purpose I /O. See 16.14.1 SPI Control Register.
Address: $0008
Bit 7654321Bit 0
Read:
PTE7 PTE6 PTE5 PTE4 PTE3 PTE2 PTE1 PTE0
Write:
Reset: Unaffected by reset
Alternative Function: SPSCK MOSI MISO SS
TACH1 TACH0 RxD TxD
Figure 17-15. Port E Data Register (PTE)
