Datasheet

ManualsBrandsNXP SEMICONDUCTORS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller QFP 64 (14x14) 8-Bit 8 MHz I/O number 51

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Table Of Contents

List of Sections
Table of Contents
List of Figures
List of Tables
Section 1. General Description
- 1.1 Contents
- 1.2 Introduction
- 1.3 Features
- 1.4 MCU Block Diagram
- 1.5 Pin Assignments
- 1.6 Pin Functions
- 1.7 I/O Pin Summary
- 1.8 Signal Name Conventions
- 1.9 Clock Source Summary
Section 2. Memory Map
- 2.1 Contents
- 2.2 Introduction
- 2.3 Unimplemented Memory Locations
- 2.4 Reserved Memory Locations
- 2.5 Input/Output (I/O) Section
Section 3. Random-Access Memory (RAM)
- 3.1 Contents
- 3.2 Introduction
- 3.3 Functional Description
Section 4. FLASH Memory
- 4.1 Contents
- 4.2 Introduction
- 4.3 Functional Description
- 4.4 FLASH Control Register
- 4.5 FLASH Page Erase Operation
- 4.6 FLASH Mass Erase Operation
- 4.7 FLASH Program/Read Operation
- 4.8 FLASH Block Protection
  - 4.8.1 FLASH Block Protect Register
- 4.9 Wait Mode
- 4.10 Stop Mode
Section 5. EEPROM
- 5.1 Contents
- 5.2 Introduction
- 5.3 Features
- 5.4 Functional Description
- 5.5 EEPROM Configuration
- 5.6 EEPROM Timebase Requirements
- 5.7 EEPROM Security Options
- 5.8 EEPROM Block Protection
- 5.9 EEPROM Programming and Erasing
  - 5.9.1 EEPROM Programming
  - 5.9.2 EEPROM Erasing
- 5.10 Low Power Modes
  - 5.10.1 Wait Mode
  - 5.10.2 Stop Mode
- 5.11 EEPROM Registers
Section 6. Configuration Register (CONFIG)
- 6.1 Contents
- 6.2 Introduction
- 6.3 Functional description
- 6.4 Configuration Register 1
- 6.5 Configuration Register 2
Section 7. Central Processor Unit (CPU)
- 7.1 Contents
- 7.2 Introduction
- 7.3 Features
- 7.4 CPU Registers
- 7.5 Arithmetic/Logic Unit (ALU)
- 7.6 Low-Power Modes
  - 7.6.1 Wait Mode
  - 7.6.2 Stop Mode
- 7.7 CPU During Break Interrupts
- 7.8 Instruction Set Summary
- 7.9 Opcode Map
Section 8. System Integration Module (SIM)
- 8.1 Contents
- 8.2 Introduction
- 8.3 SIM Bus Clock Control and Generation
- 8.4 Reset and System Initialization
  - 8.4.1 External Pin Reset
  - 8.4.2 Active Resets from Internal Sources
- 8.5 SIM Counter
- 8.6 Exception Control
- 8.7 Low-Power Modes
  - 8.7.1 Wait Mode
  - 8.7.2 Stop Mode
- 8.8 SIM Registers
Section 9. Clock Generator Module (CGM)
- 9.1 Contents
- 9.2 Introduction
- 9.3 Features
- 9.4 Functional Description
- 9.5 I/O Signals
- 9.6 CGM Registers
- 9.7 Interrupts
- 9.8 Low-Power Modes
  - 9.8.1 Wait Mode
  - 9.8.2 Stop Mode
- 9.9 CGM During Break Interrupts
- 9.10 Acquisition/Lock Time Specifications
Section 10. Monitor ROM (MON)
- 10.1 Contents
- 10.2 Introduction
- 10.3 Features
- 10.4 Functional Description
- 10.5 Security
- 10.6 Extended Security
Section 11. Timer Interface Module A (TIMA)
- 11.1 Contents
- 11.2 Introduction
- 11.3 Features
- 11.4 Pin Name Conventions
- 11.5 Functional Description
- 11.6 Interrupts
- 11.7 Low-Power Modes
  - 11.7.1 Wait Mode
  - 11.7.2 Stop Mode
- 11.8 TIMA During Break Interrupts
- 11.9 I/O Signals
  - 11.9.1 TIMA Clock Pin
  - 11.9.2 TIMA Channel I/O Pins
- 11.10 I/O Registers
Section 12. Timer Interface Module B (TIMB)
- 12.1 Contents
- 12.2 Introduction
- 12.3 Features
- 12.4 Pin Name Conventions
- 12.5 Functional Description
- 12.6 Interrupts
- 12.7 Low-Power Modes
  - 12.7.1 Wait Mode
  - 12.7.2 Stop Mode
- 12.8 TIMB During Break Interrupts
- 12.9 I/O Signals
  - 12.9.1 TIMB Clock Pin
  - 12.9.2 TIMB Channel I/O Pins
- 12.10 I/O Registers
Section 13. Programmable Interrupt Timer (PIT)
- 13.1 Contents
- 13.2 Introduction
- 13.3 Features
- 13.4 Functional Description
  - 13.4.1 PIT Counter Prescaler
- 13.5 Low-Power Modes
  - 13.5.1 Wait Mode
  - 13.5.2 Stop Mode
- 13.6 PIT During Break Interrupts
- 13.7 I/O Registers
Section 14. Analog-to-Digital Converter (ADC)
- 14.1 Contents
- 14.2 Introduction
- 14.3 Features
- 14.4 Functional Description
- 14.5 Interrupts
- 14.6 Low-Power Modes
  - 14.6.1 Wait Mode
  - 14.6.2 Stop Mode
- 14.7 I/O Signals
- 14.8 I/O Registers
Section 15. Serial Communications Interface Module (SCI)
- 15.1 Contents
- 15.2 Introduction
- 15.3 Features
- 15.4 Pin Name Conventions
- 15.5 Functional Description
- 15.6 Low-Power Modes
  - 15.6.1 Wait Mode
  - 15.6.2 Stop Mode
- 15.7 SCI During Break Module Interrupts
- 15.8 I/O Signals
  - 15.8.1 PTE0/TxD (Transmit Data)
  - 15.8.2 PTE1/RxD (Receive Data)
- 15.9 I/O Registers
Section 16. Serial Peripheral Interface Module (SPI)
- 16.1 Contents
- 16.2 Introduction
- 16.3 Features
- 16.4 Pin Name Conventions and I/O Register Addresses
- 16.5 Functional Description
  - 16.5.1 Master Mode
  - 16.5.2 Slave Mode
- 16.6 Transmission Formats
- 16.7 Queuing Transmission Data
- 16.8 Error Conditions
  - 16.8.1 Overflow Error
  - 16.8.2 Mode Fault Error
- 16.9 Interrupts
- 16.10 Resetting the SPI
- 16.11 Low-Power Modes
  - 16.11.1 Wait Mode
  - 16.11.2 Stop Mode
- 16.12 SPI During Break Interrupts
- 16.13 I/O Signals
- 16.14 I/O Registers
Section 17. Input/Output (I/O) Ports
- 17.1 Contents
- 17.2 Introduction
- 17.3 Port A
  - 17.3.1 Port A Data Register (PTA)
  - 17.3.2 Data Direction Register A (DDRA)
- 17.4 Port B
  - 17.4.1 Port B Data Register (PTB)
  - 17.4.2 Data Direction Register B (DDRB)
- 17.5 Port C
  - 17.5.1 Port C Data Register (PTC)
  - 17.5.2 Data Direction Register C (DDRC)
- 17.6 Port D
- 17.7 Port E
  - 17.7.1 Port E Data Register (PTE)
  - 17.7.2 Data Direction Register E (DDRE)
- 17.8 Port F
- 17.9 Port G
  - 17.9.1 Port G Data Register (PTG)
  - 17.9.2 Data Direction Register G (DDRG)
- 17.10 Port H
  - 17.10.1 Port H Data Register (PTH)
  - 17.10.2 Data Direction Register H (DDRH)
Section 18. External Interrupt (IRQ)
- 18.1 Contents
- 18.2 Introduction
- 18.3 Features
- 18.4 Functional Description
  - 18.4.1 IRQ Pin
- 18.5 IRQ Status and Control Register (ISCR)
- 18.6 IRQ Module During Break Interrupts
Section 19. Keyboard Interrupt Module (KBI)
- 19.1 Contents
- 19.2 Introduction
- 19.3 Features
- 19.4 I/O Pins
- 19.5 Functional Description
- 19.6 Wait Mode
- 19.7 Stop Mode
- 19.8 Keyboard Module During Break Interrupts
Section 20. Computer Operating Properly (COP)
- 20.1 Contents
- 20.2 Introduction
- 20.3 Functional Description
- 20.4 I/O Signals
- 20.5 COP Control Register
- 20.6 Interrupts
- 20.7 Monitor Mode
- 20.8 Low-Power Modes
  - 20.8.1 Wait Mode
  - 20.8.2 Stop Mode
- 20.9 COP Module During Break Mode
Section 21. Low-Voltage Inhibit (LVI)
- 21.1 Contents
- 21.2 Introduction
- 21.3 Features
- 21.4 Functional Description
- 21.5 LVI Status Register (LVISR)
- 21.6 LVI Interrupts
- 21.7 Low-Power Modes
  - 21.7.1 Wait Mode
  - 21.7.2 Stop Mode
Section 22. Break Module (BRK)
- 22.1 Contents
- 22.2 Introduction
- 22.3 Features
- 22.4 Functional Description
- 22.5 Low-Power Modes
  - 22.5.1 Wait Mode
  - 22.5.2 Stop Mode
- 22.6 Break Module Registers
Section 23. Electrical Specifications
- 23.1 Contents
- 23.2 Introduction
- 23.3 Absolute Maximum Ratings
- 23.4 Functional Operating Range
- 23.5 Thermal Characteristics
- 23.6 5.0-V DC Electrical Characteristics
- 23.7 EEPROM and Memory Characteristics
- 23.8 5.0-V Control Timing
- 23.9 Timer Interface Module Characteristics
- 23.10 ADC Characteristics
- 23.11 SPI Characteristics
- 23.12 Clock Generation Module Characteristics
- 23.13 FLASH Memory Characteristics
Section 24. Mechanical Specifications
- 24.1 Contents
- 24.2 Introduction
- 24.3 64-Pin Plastic Quad Flat Pack (QFP)
Section 25. Ordering Information
- 25.1 Contents
- 25.2 Introduction
- 25.3 MC Order Numbers

Serial Communications Interface Module (SCI)

MC68HC908AB32 — Rev. 1.1 Technical Data

Freescale Semiconductor Serial Communications Interface Module (SCI)

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Figure 15-5. SCI Receiver Block Diagram

ALL 1s

ALL 0s

WAKE

ILTY

PEN

PTY

BKF

RPF

H876543210L

11-BIT

RECEIVE SHIFT REGISTER

STOP

START

DATA

RECOVERY

SCRF

ORIE

NEIE

FEIE

PEIE

SCRIE

SCRF

ILIE

IDLE

WAKEUP

LOGIC

PARITY

CHECKING

MSB

ERROR CPU INTERRUPT REQUEST

DMA SERVICE REQUEST

CPU INTERRUPT REQUEST

SCI DATA REGISTER

ORIE

NEIE

FEIE

PEIE

SCRIE

ILIE

RWU

SCRF

IDLE

PTE1/RxD

INTERNAL BUS

PRE-

SCALER

BAUD

DIVIDER

÷ 4 ÷ 16

SCP1

SCP0

SCR2

SCR1

SCR0

SCRIE

CGMXCLK