Datasheet

Programmable Interrupt Timer (PIT)
MC68HC908AB32 — Rev. 1.1 Technical Data
Freescale Semiconductor Programmable Interrupt Timer (PIT)
227
PPS[2:0] — PIT Prescaler Select Bits
These read/write bits select one of the seven prescaler outputs as the
input to the PIT counter as Table 13-1 shows. Reset clears the
PPS[2:0] bits.
13.7.2 PIT Counter Registers
The two read-only PIT counter registers contain the high and low bytes
of the value in the PIT counter. Reading the high byte (PCNTH) latches
the contents of the low byte (PCNTL) into a buffer. Subsequent reads of
PCNTH do not affect the latched PCNTL value until PCNTL is read.
Reset clears the PIT counter registers. Setting the PIT reset bit (PRST)
also clears the PIT counter registers.
NOTE: If you read PCNTH during a break interrupt, be sure to unlatch PCNTL
by reading PCNTL before exiting the break interrupt. Otherwise, PCNTL
retains the value latched during the break.
Table 13-1. PIT Prescaler Selection
PPS2 PPS1 PPS0 PIT Clock Source
0 0 0 Internal Bus Clock ÷1
0 0 1 Internal Bus Clock ÷ 2
0 1 0 Internal Bus Clock ÷ 4
0 1 1 Internal Bus Clock ÷ 8
1 0 0 Internal Bus Clock ÷ 16
1 0 1 Internal Bus Clock ÷ 32
1 1 0 Internal Bus Clock ÷ 64
1 1 1 Internal Bus Clock ÷ 64
Address: $004C
Bit 7654321Bit 0
Read: Bit 15 14 13 12 11 10 9 Bit 8
Write:
Reset:00000000
= Unimplemented
Figure 13-4. PIT Counter Register High (PCNTH)