Datasheet

Programmable Interrupt Timer (PIT)
MC68HC908AB32 — Rev. 1.1 Technical Data
Freescale Semiconductor Programmable Interrupt Timer (PIT)
223
13.4.1 PIT Counter Prescaler
The clock source can be one of the seven prescaler outputs. The
prescaler generates seven clock rates from the internal bus clock. The
prescaler select bits, PPS[2:0] in the status and control register select
the PIT clock source.
The value in the PIT counter modulo registers and the selected prescaler
output determines the frequency of the Periodic Interrupt. The PIT
overflow flag (POF) is set when the PIT counter value rolls over to $0000
after matching the value in the PIT counter modulo registers. The PIT
interrupt enable bit, POIE, enables PIT overflow CPU interrupt requests.
POF and POIE are in the PIT status and control register.
Addr.Register Name Bit 7654321Bit 0
$004B
PIT Status and Control
Register
(PSC)
Read: POF
POIE PSTOP
00
PPS2 PPS1 PPS0
Write: 0 PRST
Reset:00100000
$004C
PIT Counter Register High
(PCNTH)
Read: Bit 15 14 13 12 11 10 9 Bit 8
Write:
Reset:00000000
$004D
PIT Counter Register Low
(PCNTL)
Read: Bit 7 654321Bit 0
Write:
Reset:00000000
$004E
PIT Counter Modulo
Register High
(PMODH)
Read:
Bit 15 14 13 12 11 10 9 Bit 8
Write:
Reset:11111111
$004F
PIT Counter Modulo
Register Low
(PMODL)
Read:
Bit 7654321Bit 0
Write:
Reset:11111111
= Unimplemented
Figure 13-2. PIT I/O Register Summary