Datasheet

Clock Generator Module (CGM)
MC68HC908AB32 — Rev. 1.1 Technical Data
Freescale Semiconductor Clock Generator Module (CGM)
155
9.10.4 Reaction Time Calculation
The actual acquisition and lock times can be calculated using the
equations below. These equations yield nominal values under the
following conditions:
• Correct selection of filter capacitor, C
F
,
(see 9.10.3 Choosing a Filter Capacitor)
• Room temperature operation
• Negligible external leakage on CGMXFC
• Negligible noise
The K factor in the equations is derived from internal PLL parameters.
K
ACQ
is the K factor when the PLL is configured in acquisition mode, and
K
TRK
is the K factor when the PLL is configured in tracking mode. See
9.4.2.2 Acquisition and Tracking Modes.
Note the inverse proportionality between the lock time and the reference
frequency.
In automatic bandwidth control mode the acquisition and lock times are
quantized into units based on the reference frequency. See 9.4.2.3
Manual and Automatic PLL Bandwidth Modes. A certain number of
clock cycles, n
ACQ
, is required to ascertain whether the PLL is within the
tracking mode entry tolerance ∆
TRK
, before exiting acquisition mode.
Also, a certain number of clock cycles, n
TRK
, is required to ascertain
t
ACQ
V
DDA
f
RDV
-------------


8
K
ACQ
-------------


=
t
AL
V
DDA
f
RDV
-------------


4
K
TRK
------------


=
t
LOCK
t
ACQ
t
AL
+=