Datasheet

Clock Generator Module (CGM)
MC68HC908AB32 — Rev. 1.1 Technical Data
Freescale Semiconductor Clock Generator Module (CGM)
143
9.5.6 Crystal Output Frequency Signal (CGMXCLK)
CGMXCLK is the crystal oscillator output signal. It runs at the full speed
of the crystal (f
XCLK
) and is generated directly from the crystal oscillator
circuit. Figure 9-3 shows only the logical relation of CGMXCLK to OSC1
and OSC2 and may not represent the actual circuitry. The duty cycle of
CGMXCLK is unknown and may depend on the crystal and other
external factors. Also, the frequency and amplitude of CGMXCLK can be
unstable at start-up.
9.5.7 CGM Base Clock Output (CGMOUT)
CGMOUT is the clock output of the CGM. This signal goes to the SIM,
which generates the MCU clocks. CGMOUT is a 50% duty cycle clock
running at twice the bus frequency. CGMOUT is software programmable
to be either the oscillator output (CGMXCLK) divided by two or the VCO
clock (CGMVCLK) divided by two.
9.5.8 CGM CPU Interrupt (CGMINT)
CGMINT is the interrupt signal generated by the PLL lock detector.
9.6 CGM Registers
The following registers control and monitor operation of the CGM:
• PLL control register (PCTL). (See 9.6.1 PLL Control Register
(PCTL))
• PLL bandwidth control register (PBWC). (See 9.6.2 PLL
Bandwidth Control Register (PBWC))
• PLL programming register (PPG). (See 9.6.3 PLL Programming
Register (PPG))
Figure 9-4 is a summary of the CGM registers.