Datasheet

Clock Generator Module (CGM)
Technical Data MC68HC908AB32 — Rev. 1.1
142 Clock Generator Module (CGM) Freescale Semiconductor
9.5 I/O Signals
The following paragraphs describe the CGM I/O signals.
9.5.1 Crystal Amplifier Input Pin (OSC1)
The OSC1 pin is an input to the crystal oscillator amplifier.
9.5.2 Crystal Amplifier Output Pin (OSC2)
The OSC2 pin is the output of the crystal oscillator inverting amplifier.
9.5.3 External Filter Capacitor Pin (CGMXFC)
The CGMXFC pin is required by the loop filter to filter out phase
corrections. A small external capacitor is connected to this pin.
NOTE: To prevent noise problems, C
F
should be placed as close to the
CGMXFC pin as possible, with minimum routing distances and no
routing of other signals across the C
F
connection.
9.5.4 PLL Analog Power Pin (V
DDA
)
V
DDA
is a power pin used by the analog portions of the PLL. The pin
should be connected to the same voltage potential as the V
DD
pin.
NOTE: Route V
DDA
carefully for maximum noise immunity and place bypass
capacitors as close as possible to the package.
9.5.5 Oscillator Enable Signal (SIMOSCEN)
The SIMOSCEN signal comes from the system integration module (SIM)
and enables the oscillator and PLL.