Datasheet

Clock Generator Module (CGM)
MC68HC908AB32 — Rev. 1.1 Technical Data
Freescale Semiconductor Clock Generator Module (CGM)
139
5. Calculate and verify the adequacy of the VCO and bus
frequencies f
VCLK
and f
BUS
.
6. Select a VCO linear range multiplier, L.
where f
NOM
= 4.9152MHz
7. Calculate and verify the adequacy of the VCO programmed
center-of-range frequency f
VRS
.
f
VRS
= (L)f
NOM
8. Verify the choice of N and L by comparing f
VCLK
to f
VRS
and
f
VCLKDES
. For proper operation, f
VCLK
must be within the
application’s tolerance of f
VCLKDES
, and f
VRS
must be as close as
possible to f
VCLK
.
NOTE: Exceeding the recommended maximum bus frequency or VCO
frequency can cause the MCU to “crash”.
9. Program the PLL registers accordingly:
a. In the upper 4 bits of the PLL programming register (PPG),
program the binary equivalent of N.
b. In the lower 4 bits of the PLL programming register (PPG),
program the binary equivalent of L.
9.4.2.5 Special Programming Exceptions
The programming method described in 9.4.2.4 Programming the PLL
does not account for two possible exceptions — a value of zero for N or
L is meaningless when used in the equations given. To account for these
exceptions:
f
VCLK
Nf
RCLK
×=
f
BUS
f
VCLK
()4⁄=
L round
f
VCLK
f
NOM
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