Datasheet

Clock Generator Module (CGM)
Technical Data MC68HC908AB32 — Rev. 1.1
132 Clock Generator Module (CGM) Freescale Semiconductor
9.8.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150
9.8.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151
9.9 CGM During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . .151
9.10 Acquisition/Lock Time Specifications . . . . . . . . . . . . . . . . . . .151
9.10.1 Acquisition/Lock Time Definitions. . . . . . . . . . . . . . . . . . . .152
9.10.2 Parametric Influences On Reaction Time. . . . . . . . . . . . . .153
9.10.3 Choosing a Filter Capacitor . . . . . . . . . . . . . . . . . . . . . . . .154
9.10.4 Reaction Time Calculation . . . . . . . . . . . . . . . . . . . . . . . . .155
9.2 Introduction
This section describes the clock generator module (CGM). The CGM
generates the crystal clock signal, CGMXCLK, which operates at the
frequency of the crystal. The CGM also generates the base clock signal,
CGMOUT, from which the system integration module (SIM) derives the
system clocks. CGMOUT is based on either the crystal clock divided by
two or the phase-locked loop (PLL) clock, CGMVCLK, divided by two.
The PLL is a frequency generator designed for use with 1MHz to 8MHz
crystals or ceramic resonators. The PLL can generate an 8MHz bus
frequency without using a higher frequency crystal.
9.3 Features
Features of the CGM include the following:
• Phase-locked loop with output frequency in integer multiples of the
crystal reference
• Programmable hardware voltage-controlled oscillator (VCO) for
low-jitter operation
• Automatic bandwidth control mode for low-jitter operation
• Automatic frequency lock detector
• CPU interrupt on entry or exit from locked condition