Datasheet

System Integration Module (SIM)
MC68HC908AB32 — Rev. 1.1 Technical Data
Freescale Semiconductor System Integration Module (SIM)
119
8.6.1 Interrupts
At the beginning of an interrupt, the CPU saves the CPU register
contents onto the stack and sets the interrupt mask (I-bit) to prevent
additional interrupts. At the end of an interrupt, the RTI instruction
recovers the CPU register contents from the stack so that normal
processing can resume. Figure 8-8 shows interrupt entry timing, and
Figure 8-9 shows interrupt recovery timing.
Figure 8-8. Interrupt Entry Timing
Figure 8-9. Interrupt Recovery Timing
Interrupts are latched, and arbitration is performed in the SIM at the start
of interrupt processing. The arbitration result is a constant that the CPU
uses to determine which vector to fetch. Once an interrupt is latched by
the SIM, no other interrupt may take precedence, regardless of priority,
until the latched interrupt is serviced (or the I-bit is cleared).
(See Figure 8-10.)
MODULE
IDB
R/W
INTERRUPT
DUMMY
SP SP – 1 SP – 2 SP – 3 SP – 4 VECT H VECT L START ADDR
IAB
DUMMY PC – 1[7:0] PC – 1[15:8] X A CCR V DATA H V DATA L OPCODE
I-BIT
MODULE
IDB
R/W
INTERRUPT
SP – 4 SP – 3 SP – 2 SP – 1 SP PC PC + 1
IAB
CCR A X PC – 1[7:0] PC – 1[15:8] OPCODE OPERAND
I-BIT