Datasheet

System Integration Module (SIM)
MC68HC908AB32 — Rev. 1.1 Technical Data
Freescale Semiconductor System Integration Module (SIM)
117
8.4.2.3 Illegal Opcode Reset
The SIM decodes signals from the CPU to detect illegal instructions. An
illegal instruction sets the ILOP bit in the SIM reset status register
(SRSR) and causes a reset.
If the STOP enable bit, STOP, in the configuration register 1 (CONFIG1)
is logic 0, the SIM treats the STOP instruction as an illegal opcode and
causes an illegal opcode reset. The SIM actively pulls down the RST pin
for all internal reset sources.
8.4.2.4 Illegal Address Reset
An opcode fetch from an unmapped address generates an illegal
address reset. The SIM verifies that the CPU is fetching an opcode prior
to asserting the ILAD bit in the SIM reset status register (SRSR) and
resetting the MCU. A data fetch from an unmapped address does not
generate a reset. The SIM actively pulls down the RST pin for all internal
reset sources.
8.4.2.5 Low-Voltage Inhibit (LVI) Reset
The low-voltage inhibit module (LVI) asserts its output to the SIM when
the V
DD
voltage falls to the trip voltage, V
LVII
. The LVI bit in the SIM reset
status register (SRSR) is set, and the external reset pin (RST) is held low
while the SIM counter counts out 4096 CGMXCLK cycles. 64 CGMXCLK
cycles later, the CPU is released from reset to allow the reset vector
sequence to occur. The SIM actively pulls down the RST
pin for all
internal reset sources.
8.5 SIM Counter
The SIM counter is used by the power-on reset module (POR) and in
stop mode recovery to allow the oscillator time to stabilize before
enabling the internal bus (IBUS) clocks. The SIM counter also serves as
a prescaler for the computer operating properly (COP) module. The SIM
counter overflow supplies the clock for the COP module. The SIM
counter is 13 bits long and is clocked by the falling edge of CGMXCLK.