Datasheet

System Integration Module (SIM)
Technical Data MC68HC908AB32 — Rev. 1.1
116 System Integration Module (SIM) Freescale Semiconductor
• The RST pin is driven low during the oscillator stabilization time
• The POR bit of the SIM reset status register (SRSR) is set and all
other bits in the register are cleared
Figure 8-7. POR Recovery
8.4.2.2 Computer Operating Properly (COP) Reset
An input to the SIM is reserved for the COP reset signal. The overflow of
the COP counter causes an internal reset and sets the COP bit in the
SIM reset status register (SRSR). The SIM actively pulls down the RST
pin for all internal reset sources.
To prevent a COP module timeout, a value (any value) should be written
to location $FFFF. Writing to location $FFFF clears the COP counter and
bits 12 through 4 of the SIM counter. The SIM counter output, which
occurs at least every 2
13
– 2
4
CGMXCLK cycles, drives the COP
counter. The COP should be serviced as soon as possible out of reset
to guarantee the maximum amount of time before the first timeout.
The COP module is disabled if the RST pin or the IRQ pin is held at V
TST
while the MCU is in monitor mode. The COP module can be disabled
only through combinational logic conditioned with the high voltage signal
on the RST
or the IRQ pin. This prevents the COP from becoming
disabled as a result of external noise. During a break state, V
TST
on the
RST pin disables the COP module.
PORRST
OSC1
CGMXCLK
CGMOUT
RST
IAB
4096
CYCLES
32
CYCLES
32
CYCLES
$FFFE $FFFF