Datasheet

ManualsBrandsNXP SEMICONDUCTORS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller QFP 64 (14x14) 8-Bit 8 MHz I/O number 51

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Table Of Contents

List of Sections
Table of Contents
List of Figures
List of Tables
Section 1. General Description
- 1.1 Contents
- 1.2 Introduction
- 1.3 Features
- 1.4 MCU Block Diagram
- 1.5 Pin Assignments
- 1.6 Pin Functions
- 1.7 I/O Pin Summary
- 1.8 Signal Name Conventions
- 1.9 Clock Source Summary
Section 2. Memory Map
- 2.1 Contents
- 2.2 Introduction
- 2.3 Unimplemented Memory Locations
- 2.4 Reserved Memory Locations
- 2.5 Input/Output (I/O) Section
Section 3. Random-Access Memory (RAM)
- 3.1 Contents
- 3.2 Introduction
- 3.3 Functional Description
Section 4. FLASH Memory
- 4.1 Contents
- 4.2 Introduction
- 4.3 Functional Description
- 4.4 FLASH Control Register
- 4.5 FLASH Page Erase Operation
- 4.6 FLASH Mass Erase Operation
- 4.7 FLASH Program/Read Operation
- 4.8 FLASH Block Protection
  - 4.8.1 FLASH Block Protect Register
- 4.9 Wait Mode
- 4.10 Stop Mode
Section 5. EEPROM
- 5.1 Contents
- 5.2 Introduction
- 5.3 Features
- 5.4 Functional Description
- 5.5 EEPROM Configuration
- 5.6 EEPROM Timebase Requirements
- 5.7 EEPROM Security Options
- 5.8 EEPROM Block Protection
- 5.9 EEPROM Programming and Erasing
  - 5.9.1 EEPROM Programming
  - 5.9.2 EEPROM Erasing
- 5.10 Low Power Modes
  - 5.10.1 Wait Mode
  - 5.10.2 Stop Mode
- 5.11 EEPROM Registers
Section 6. Configuration Register (CONFIG)
- 6.1 Contents
- 6.2 Introduction
- 6.3 Functional description
- 6.4 Configuration Register 1
- 6.5 Configuration Register 2
Section 7. Central Processor Unit (CPU)
- 7.1 Contents
- 7.2 Introduction
- 7.3 Features
- 7.4 CPU Registers
- 7.5 Arithmetic/Logic Unit (ALU)
- 7.6 Low-Power Modes
  - 7.6.1 Wait Mode
  - 7.6.2 Stop Mode
- 7.7 CPU During Break Interrupts
- 7.8 Instruction Set Summary
- 7.9 Opcode Map
Section 8. System Integration Module (SIM)
- 8.1 Contents
- 8.2 Introduction
- 8.3 SIM Bus Clock Control and Generation
- 8.4 Reset and System Initialization
  - 8.4.1 External Pin Reset
  - 8.4.2 Active Resets from Internal Sources
- 8.5 SIM Counter
- 8.6 Exception Control
- 8.7 Low-Power Modes
  - 8.7.1 Wait Mode
  - 8.7.2 Stop Mode
- 8.8 SIM Registers
Section 9. Clock Generator Module (CGM)
- 9.1 Contents
- 9.2 Introduction
- 9.3 Features
- 9.4 Functional Description
- 9.5 I/O Signals
- 9.6 CGM Registers
- 9.7 Interrupts
- 9.8 Low-Power Modes
  - 9.8.1 Wait Mode
  - 9.8.2 Stop Mode
- 9.9 CGM During Break Interrupts
- 9.10 Acquisition/Lock Time Specifications
Section 10. Monitor ROM (MON)
- 10.1 Contents
- 10.2 Introduction
- 10.3 Features
- 10.4 Functional Description
- 10.5 Security
- 10.6 Extended Security
Section 11. Timer Interface Module A (TIMA)
- 11.1 Contents
- 11.2 Introduction
- 11.3 Features
- 11.4 Pin Name Conventions
- 11.5 Functional Description
- 11.6 Interrupts
- 11.7 Low-Power Modes
  - 11.7.1 Wait Mode
  - 11.7.2 Stop Mode
- 11.8 TIMA During Break Interrupts
- 11.9 I/O Signals
  - 11.9.1 TIMA Clock Pin
  - 11.9.2 TIMA Channel I/O Pins
- 11.10 I/O Registers
Section 12. Timer Interface Module B (TIMB)
- 12.1 Contents
- 12.2 Introduction
- 12.3 Features
- 12.4 Pin Name Conventions
- 12.5 Functional Description
- 12.6 Interrupts
- 12.7 Low-Power Modes
  - 12.7.1 Wait Mode
  - 12.7.2 Stop Mode
- 12.8 TIMB During Break Interrupts
- 12.9 I/O Signals
  - 12.9.1 TIMB Clock Pin
  - 12.9.2 TIMB Channel I/O Pins
- 12.10 I/O Registers
Section 13. Programmable Interrupt Timer (PIT)
- 13.1 Contents
- 13.2 Introduction
- 13.3 Features
- 13.4 Functional Description
  - 13.4.1 PIT Counter Prescaler
- 13.5 Low-Power Modes
  - 13.5.1 Wait Mode
  - 13.5.2 Stop Mode
- 13.6 PIT During Break Interrupts
- 13.7 I/O Registers
Section 14. Analog-to-Digital Converter (ADC)
- 14.1 Contents
- 14.2 Introduction
- 14.3 Features
- 14.4 Functional Description
- 14.5 Interrupts
- 14.6 Low-Power Modes
  - 14.6.1 Wait Mode
  - 14.6.2 Stop Mode
- 14.7 I/O Signals
- 14.8 I/O Registers
Section 15. Serial Communications Interface Module (SCI)
- 15.1 Contents
- 15.2 Introduction
- 15.3 Features
- 15.4 Pin Name Conventions
- 15.5 Functional Description
- 15.6 Low-Power Modes
  - 15.6.1 Wait Mode
  - 15.6.2 Stop Mode
- 15.7 SCI During Break Module Interrupts
- 15.8 I/O Signals
  - 15.8.1 PTE0/TxD (Transmit Data)
  - 15.8.2 PTE1/RxD (Receive Data)
- 15.9 I/O Registers
Section 16. Serial Peripheral Interface Module (SPI)
- 16.1 Contents
- 16.2 Introduction
- 16.3 Features
- 16.4 Pin Name Conventions and I/O Register Addresses
- 16.5 Functional Description
  - 16.5.1 Master Mode
  - 16.5.2 Slave Mode
- 16.6 Transmission Formats
- 16.7 Queuing Transmission Data
- 16.8 Error Conditions
  - 16.8.1 Overflow Error
  - 16.8.2 Mode Fault Error
- 16.9 Interrupts
- 16.10 Resetting the SPI
- 16.11 Low-Power Modes
  - 16.11.1 Wait Mode
  - 16.11.2 Stop Mode
- 16.12 SPI During Break Interrupts
- 16.13 I/O Signals
- 16.14 I/O Registers
Section 17. Input/Output (I/O) Ports
- 17.1 Contents
- 17.2 Introduction
- 17.3 Port A
  - 17.3.1 Port A Data Register (PTA)
  - 17.3.2 Data Direction Register A (DDRA)
- 17.4 Port B
  - 17.4.1 Port B Data Register (PTB)
  - 17.4.2 Data Direction Register B (DDRB)
- 17.5 Port C
  - 17.5.1 Port C Data Register (PTC)
  - 17.5.2 Data Direction Register C (DDRC)
- 17.6 Port D
- 17.7 Port E
  - 17.7.1 Port E Data Register (PTE)
  - 17.7.2 Data Direction Register E (DDRE)
- 17.8 Port F
- 17.9 Port G
  - 17.9.1 Port G Data Register (PTG)
  - 17.9.2 Data Direction Register G (DDRG)
- 17.10 Port H
  - 17.10.1 Port H Data Register (PTH)
  - 17.10.2 Data Direction Register H (DDRH)
Section 18. External Interrupt (IRQ)
- 18.1 Contents
- 18.2 Introduction
- 18.3 Features
- 18.4 Functional Description
  - 18.4.1 IRQ Pin
- 18.5 IRQ Status and Control Register (ISCR)
- 18.6 IRQ Module During Break Interrupts
Section 19. Keyboard Interrupt Module (KBI)
- 19.1 Contents
- 19.2 Introduction
- 19.3 Features
- 19.4 I/O Pins
- 19.5 Functional Description
- 19.6 Wait Mode
- 19.7 Stop Mode
- 19.8 Keyboard Module During Break Interrupts
Section 20. Computer Operating Properly (COP)
- 20.1 Contents
- 20.2 Introduction
- 20.3 Functional Description
- 20.4 I/O Signals
- 20.5 COP Control Register
- 20.6 Interrupts
- 20.7 Monitor Mode
- 20.8 Low-Power Modes
  - 20.8.1 Wait Mode
  - 20.8.2 Stop Mode
- 20.9 COP Module During Break Mode
Section 21. Low-Voltage Inhibit (LVI)
- 21.1 Contents
- 21.2 Introduction
- 21.3 Features
- 21.4 Functional Description
- 21.5 LVI Status Register (LVISR)
- 21.6 LVI Interrupts
- 21.7 Low-Power Modes
  - 21.7.1 Wait Mode
  - 21.7.2 Stop Mode
Section 22. Break Module (BRK)
- 22.1 Contents
- 22.2 Introduction
- 22.3 Features
- 22.4 Functional Description
- 22.5 Low-Power Modes
  - 22.5.1 Wait Mode
  - 22.5.2 Stop Mode
- 22.6 Break Module Registers
Section 23. Electrical Specifications
- 23.1 Contents
- 23.2 Introduction
- 23.3 Absolute Maximum Ratings
- 23.4 Functional Operating Range
- 23.5 Thermal Characteristics
- 23.6 5.0-V DC Electrical Characteristics
- 23.7 EEPROM and Memory Characteristics
- 23.8 5.0-V Control Timing
- 23.9 Timer Interface Module Characteristics
- 23.10 ADC Characteristics
- 23.11 SPI Characteristics
- 23.12 Clock Generation Module Characteristics
- 23.13 FLASH Memory Characteristics
Section 24. Mechanical Specifications
- 24.1 Contents
- 24.2 Introduction
- 24.3 64-Pin Plastic Quad Flat Pack (QFP)
Section 25. Ordering Information
- 25.1 Contents
- 25.2 Introduction
- 25.3 MC Order Numbers

MC68HC908AB32 — Rev. 1.1 Technical Data

Freescale Semiconductor Central Processor Unit (CPU)

107

Central Processor Unit (CPU)

Table 7-2. Opcode Map

Bit Manipulation Branch Read-Modify-Write Control Register/Memory

DIR DIR REL DIR INH INH IX1 SP1 IX INH INH IMM DIR EXT IX2 SP2 IX1 SP1 IX

01234569E6789ABCD9EDE9EEF

BRSET0

3DIR

BSET0

2DIR

BRA

2REL

NEG

2DIR

NEGA

1INH

NEGX

1INH

NEG

2IX1

NEG

3SP1

NEG

1IX

RTI

1INH

BGE

2REL

SUB

2IMM

SUB

2DIR

SUB

3EXT

SUB

3IX2

SUB

4SP2

SUB

2IX1

SUB

3SP1

SUB

1IX

BRCLR0

3DIR

BCLR0

2DIR

BRN

2REL

CBEQ

3DIR

CBEQA

3IMM

CBEQX

3IMM

CBEQ

3IX1+

CBEQ

4SP1

CBEQ

2IX+

RTS

1INH

BLT

2REL

CMP

2IMM

CMP

2DIR

CMP

3EXT

CMP

3IX2

CMP

4SP2

CMP

2IX1

CMP

3SP1

CMP

1IX

BRSET1

3DIR

BSET1

2DIR

BHI

2REL

MUL

1INH

DIV

1INH

NSA

1INH

DAA

1INH

BGT

2REL

SBC

2IMM

SBC

2DIR

SBC

3EXT

SBC

3IX2

SBC

4SP2

SBC

2IX1

SBC

3SP1

SBC

1IX

BRCLR1

3DIR

BCLR1

2DIR

BLS

2REL

COM

2DIR

COMA

1INH

COMX

1INH

COM

2IX1

COM

3SP1

COM

1IX

SWI

1INH

BLE

2REL

CPX

2IMM

CPX

2DIR

CPX

3EXT

CPX

3IX2

CPX

4SP2

CPX

2IX1

CPX

3SP1

CPX

1IX

BRSET2

3DIR

BSET2

2DIR

BCC

2REL

LSR

2DIR

LSRA

1INH

LSRX

1INH

LSR

2IX1

LSR

3SP1

LSR

1IX

TA P

1INH

TXS

1INH

AND

2IMM

AND

2DIR

AND

3EXT

AND

3IX2

AND

4SP2

AND

2IX1

AND

3SP1

AND

1IX

BRCLR2

3DIR

BCLR2

2DIR

BCS

2REL

STHX

2DIR

LDHX

3IMM

LDHX

2DIR

CPHX

3IMM

CPHX

2DIR

TPA

1INH

TSX

1INH

BIT

2IMM

BIT

2DIR

BIT

3EXT

BIT

3IX2

BIT

4SP2

BIT

2IX1

BIT

3SP1

BIT

1IX

BRSET3

3DIR

BSET3

2DIR

BNE

2REL

ROR

2DIR

RORA

1INH

RORX

1INH

ROR

2IX1

ROR

3SP1

ROR

1IX

PULA

1INH

LDA

2IMM

LDA

2DIR

LDA

3EXT

LDA

3IX2

LDA

4SP2

LDA

2IX1

LDA

3SP1

LDA

1IX

BRCLR3

3DIR

BCLR3

2DIR

BEQ

2REL

ASR

2DIR

ASRA

1INH

ASRX

1INH

ASR

2IX1

ASR

3SP1

ASR

1IX

PSHA

1INH

TA X

1INH

AIS

2IMM

STA

2DIR

STA

3EXT

STA

3IX2

STA

4SP2

STA

2IX1

STA

3SP1

STA

1IX

BRSET4

3DIR

BSET4

2DIR

BHCC

2REL

LSL

2DIR

LSLA

1INH

LSLX

1INH

LSL

2IX1

LSL

3SP1

LSL

1IX

PULX

1INH

CLC

1INH

EOR

2IMM

EOR

2DIR

EOR

3EXT

EOR

3IX2

EOR

4SP2

EOR

2IX1

EOR

3SP1

EOR

1IX

BRCLR4

3DIR

BCLR4

2DIR

BHCS

2REL

ROL

2DIR

ROLA

1INH

ROLX

1INH

ROL

2IX1

ROL

3SP1

ROL

1IX

PSHX

1INH

SEC

1INH

ADC

2IMM

ADC

2DIR

ADC

3EXT

ADC

3IX2

ADC

4SP2

ADC

2IX1

ADC

3SP1

ADC

1IX

BRSET5

3DIR

BSET5

2DIR

BPL

2REL

DEC

2DIR

DECA

1INH

DECX

1INH

DEC

2IX1

DEC

3SP1

DEC

1IX

PULH

1INH

CLI

1INH

ORA

2IMM

ORA

2DIR

ORA

3EXT

ORA

3IX2

ORA

4SP2

ORA

2IX1

ORA

3SP1

ORA

1IX

BRCLR5

3DIR

BCLR5

2DIR

BMI

2REL

DBNZ

3DIR

DBNZA

2INH

DBNZX

2INH

DBNZ

3IX1

DBNZ

4SP1

DBNZ

2IX

PSHH

1INH

SEI

1INH

ADD

2IMM

ADD

2DIR

ADD

3EXT

ADD

3IX2

ADD

4SP2

ADD

2IX1

ADD

3SP1

ADD

1IX

BRSET6

3DIR

BSET6

2DIR

BMC

2REL

INC

2DIR

INCA

1INH

INCX

1INH

INC

2IX1

INC

3SP1

INC

1IX

CLRH

1INH

RSP

1INH

JMP

2DIR

JMP

3EXT

JMP

3IX2

JMP

2IX1

JMP

1IX

BRCLR6

3DIR

BCLR6

2DIR

BMS

2REL

TST

2DIR

TSTA

1INH

TSTX

1INH

TST

2IX1

TST

3SP1

TST

1IX

NOP

1INH

BSR

2REL

JSR

2DIR

JSR

3EXT

JSR

3IX2

JSR

2IX1

JSR

1IX

BRSET7

3DIR

BSET7

2DIR

BIL

2REL

MOV

3DD

MOV

2DIX+

MOV

3IMD

MOV

2IX+D

STOP

1INH

LDX

2IMM

LDX

2DIR

LDX

3EXT

LDX

3IX2

LDX

4SP2

LDX

2IX1

LDX

3SP1

LDX

1IX

BRCLR7

3DIR

BCLR7

2DIR

BIH

2REL

CLR

2DIR

CLRA

1INH

CLRX

1INH

CLR

2IX1

CLR

3SP1

CLR

1IX

WAIT

1INH

TXA

1INH

AIX

2IMM

STX

2DIR

STX

3EXT

STX

3IX2

STX

4SP2

STX

2IX1

STX

3SP1

STX

1IX

INH Inherent REL Relative SP1 Stack Pointer, 8-Bit Offset

IMM Immediate IX Indexed, No Offset SP2 Stack Pointer, 16-Bit Offset

DIR Direct IX1 Indexed, 8-Bit Offset IX+ Indexed, No Offset with

EXT Extended IX2 Indexed, 16-Bit Offset Post Increment

DD Direct-Direct IMD Immediate-Direct IX1+ Indexed, 1-Byte Offset with

IX+D Indexed-Direct DIX+ Direct-Indexed Post Increment

*Pre-byte for stack pointer indexed instructions

0 High Byte of Opcode in Hexadecimal

Low Byte of Opcode in Hexadecimal 0

BRSET0

3DIR

Cycles

Opcode Mnemonic

Number of Bytes / Addressing Mode

MSB

LSB

MSB

LSB