Datasheet

ManualsBrandsNXP SEMICONDUCTORS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller QFP 64 (14x14) 8-Bit 8 MHz I/O number 51

Table Of Contents

List of Sections
Table of Contents
List of Figures
List of Tables
Section 1. General Description
- 1.1 Contents
- 1.2 Introduction
- 1.3 Features
- 1.4 MCU Block Diagram
- 1.5 Pin Assignments
- 1.6 Pin Functions
- 1.7 I/O Pin Summary
- 1.8 Signal Name Conventions
- 1.9 Clock Source Summary
Section 2. Memory Map
- 2.1 Contents
- 2.2 Introduction
- 2.3 Unimplemented Memory Locations
- 2.4 Reserved Memory Locations
- 2.5 Input/Output (I/O) Section
Section 3. Random-Access Memory (RAM)
- 3.1 Contents
- 3.2 Introduction
- 3.3 Functional Description
Section 4. FLASH Memory
- 4.1 Contents
- 4.2 Introduction
- 4.3 Functional Description
- 4.4 FLASH Control Register
- 4.5 FLASH Page Erase Operation
- 4.6 FLASH Mass Erase Operation
- 4.7 FLASH Program/Read Operation
- 4.8 FLASH Block Protection
  - 4.8.1 FLASH Block Protect Register
- 4.9 Wait Mode
- 4.10 Stop Mode
Section 5. EEPROM
- 5.1 Contents
- 5.2 Introduction
- 5.3 Features
- 5.4 Functional Description
- 5.5 EEPROM Configuration
- 5.6 EEPROM Timebase Requirements
- 5.7 EEPROM Security Options
- 5.8 EEPROM Block Protection
- 5.9 EEPROM Programming and Erasing
  - 5.9.1 EEPROM Programming
  - 5.9.2 EEPROM Erasing
- 5.10 Low Power Modes
  - 5.10.1 Wait Mode
  - 5.10.2 Stop Mode
- 5.11 EEPROM Registers
Section 6. Configuration Register (CONFIG)
- 6.1 Contents
- 6.2 Introduction
- 6.3 Functional description
- 6.4 Configuration Register 1
- 6.5 Configuration Register 2
Section 7. Central Processor Unit (CPU)
- 7.1 Contents
- 7.2 Introduction
- 7.3 Features
- 7.4 CPU Registers
- 7.5 Arithmetic/Logic Unit (ALU)
- 7.6 Low-Power Modes
  - 7.6.1 Wait Mode
  - 7.6.2 Stop Mode
- 7.7 CPU During Break Interrupts
- 7.8 Instruction Set Summary
- 7.9 Opcode Map
Section 8. System Integration Module (SIM)
- 8.1 Contents
- 8.2 Introduction
- 8.3 SIM Bus Clock Control and Generation
- 8.4 Reset and System Initialization
  - 8.4.1 External Pin Reset
  - 8.4.2 Active Resets from Internal Sources
- 8.5 SIM Counter
- 8.6 Exception Control
- 8.7 Low-Power Modes
  - 8.7.1 Wait Mode
  - 8.7.2 Stop Mode
- 8.8 SIM Registers
Section 9. Clock Generator Module (CGM)
- 9.1 Contents
- 9.2 Introduction
- 9.3 Features
- 9.4 Functional Description
- 9.5 I/O Signals
- 9.6 CGM Registers
- 9.7 Interrupts
- 9.8 Low-Power Modes
  - 9.8.1 Wait Mode
  - 9.8.2 Stop Mode
- 9.9 CGM During Break Interrupts
- 9.10 Acquisition/Lock Time Specifications
Section 10. Monitor ROM (MON)
- 10.1 Contents
- 10.2 Introduction
- 10.3 Features
- 10.4 Functional Description
- 10.5 Security
- 10.6 Extended Security
Section 11. Timer Interface Module A (TIMA)
- 11.1 Contents
- 11.2 Introduction
- 11.3 Features
- 11.4 Pin Name Conventions
- 11.5 Functional Description
- 11.6 Interrupts
- 11.7 Low-Power Modes
  - 11.7.1 Wait Mode
  - 11.7.2 Stop Mode
- 11.8 TIMA During Break Interrupts
- 11.9 I/O Signals
  - 11.9.1 TIMA Clock Pin
  - 11.9.2 TIMA Channel I/O Pins
- 11.10 I/O Registers
Section 12. Timer Interface Module B (TIMB)
- 12.1 Contents
- 12.2 Introduction
- 12.3 Features
- 12.4 Pin Name Conventions
- 12.5 Functional Description
- 12.6 Interrupts
- 12.7 Low-Power Modes
  - 12.7.1 Wait Mode
  - 12.7.2 Stop Mode
- 12.8 TIMB During Break Interrupts
- 12.9 I/O Signals
  - 12.9.1 TIMB Clock Pin
  - 12.9.2 TIMB Channel I/O Pins
- 12.10 I/O Registers
Section 13. Programmable Interrupt Timer (PIT)
- 13.1 Contents
- 13.2 Introduction
- 13.3 Features
- 13.4 Functional Description
  - 13.4.1 PIT Counter Prescaler
- 13.5 Low-Power Modes
  - 13.5.1 Wait Mode
  - 13.5.2 Stop Mode
- 13.6 PIT During Break Interrupts
- 13.7 I/O Registers
Section 14. Analog-to-Digital Converter (ADC)
- 14.1 Contents
- 14.2 Introduction
- 14.3 Features
- 14.4 Functional Description
- 14.5 Interrupts
- 14.6 Low-Power Modes
  - 14.6.1 Wait Mode
  - 14.6.2 Stop Mode
- 14.7 I/O Signals
- 14.8 I/O Registers
Section 15. Serial Communications Interface Module (SCI)
- 15.1 Contents
- 15.2 Introduction
- 15.3 Features
- 15.4 Pin Name Conventions
- 15.5 Functional Description
- 15.6 Low-Power Modes
  - 15.6.1 Wait Mode
  - 15.6.2 Stop Mode
- 15.7 SCI During Break Module Interrupts
- 15.8 I/O Signals
  - 15.8.1 PTE0/TxD (Transmit Data)
  - 15.8.2 PTE1/RxD (Receive Data)
- 15.9 I/O Registers
Section 16. Serial Peripheral Interface Module (SPI)
- 16.1 Contents
- 16.2 Introduction
- 16.3 Features
- 16.4 Pin Name Conventions and I/O Register Addresses
- 16.5 Functional Description
  - 16.5.1 Master Mode
  - 16.5.2 Slave Mode
- 16.6 Transmission Formats
- 16.7 Queuing Transmission Data
- 16.8 Error Conditions
  - 16.8.1 Overflow Error
  - 16.8.2 Mode Fault Error
- 16.9 Interrupts
- 16.10 Resetting the SPI
- 16.11 Low-Power Modes
  - 16.11.1 Wait Mode
  - 16.11.2 Stop Mode
- 16.12 SPI During Break Interrupts
- 16.13 I/O Signals
- 16.14 I/O Registers
Section 17. Input/Output (I/O) Ports
- 17.1 Contents
- 17.2 Introduction
- 17.3 Port A
  - 17.3.1 Port A Data Register (PTA)
  - 17.3.2 Data Direction Register A (DDRA)
- 17.4 Port B
  - 17.4.1 Port B Data Register (PTB)
  - 17.4.2 Data Direction Register B (DDRB)
- 17.5 Port C
  - 17.5.1 Port C Data Register (PTC)
  - 17.5.2 Data Direction Register C (DDRC)
- 17.6 Port D
- 17.7 Port E
  - 17.7.1 Port E Data Register (PTE)
  - 17.7.2 Data Direction Register E (DDRE)
- 17.8 Port F
- 17.9 Port G
  - 17.9.1 Port G Data Register (PTG)
  - 17.9.2 Data Direction Register G (DDRG)
- 17.10 Port H
  - 17.10.1 Port H Data Register (PTH)
  - 17.10.2 Data Direction Register H (DDRH)
Section 18. External Interrupt (IRQ)
- 18.1 Contents
- 18.2 Introduction
- 18.3 Features
- 18.4 Functional Description
  - 18.4.1 IRQ Pin
- 18.5 IRQ Status and Control Register (ISCR)
- 18.6 IRQ Module During Break Interrupts
Section 19. Keyboard Interrupt Module (KBI)
- 19.1 Contents
- 19.2 Introduction
- 19.3 Features
- 19.4 I/O Pins
- 19.5 Functional Description
- 19.6 Wait Mode
- 19.7 Stop Mode
- 19.8 Keyboard Module During Break Interrupts
Section 20. Computer Operating Properly (COP)
- 20.1 Contents
- 20.2 Introduction
- 20.3 Functional Description
- 20.4 I/O Signals
- 20.5 COP Control Register
- 20.6 Interrupts
- 20.7 Monitor Mode
- 20.8 Low-Power Modes
  - 20.8.1 Wait Mode
  - 20.8.2 Stop Mode
- 20.9 COP Module During Break Mode
Section 21. Low-Voltage Inhibit (LVI)
- 21.1 Contents
- 21.2 Introduction
- 21.3 Features
- 21.4 Functional Description
- 21.5 LVI Status Register (LVISR)
- 21.6 LVI Interrupts
- 21.7 Low-Power Modes
  - 21.7.1 Wait Mode
  - 21.7.2 Stop Mode
Section 22. Break Module (BRK)
- 22.1 Contents
- 22.2 Introduction
- 22.3 Features
- 22.4 Functional Description
- 22.5 Low-Power Modes
  - 22.5.1 Wait Mode
  - 22.5.2 Stop Mode
- 22.6 Break Module Registers
Section 23. Electrical Specifications
- 23.1 Contents
- 23.2 Introduction
- 23.3 Absolute Maximum Ratings
- 23.4 Functional Operating Range
- 23.5 Thermal Characteristics
- 23.6 5.0-V DC Electrical Characteristics
- 23.7 EEPROM and Memory Characteristics
- 23.8 5.0-V Control Timing
- 23.9 Timer Interface Module Characteristics
- 23.10 ADC Characteristics
- 23.11 SPI Characteristics
- 23.12 Clock Generation Module Characteristics
- 23.13 FLASH Memory Characteristics
Section 24. Mechanical Specifications
- 24.1 Contents
- 24.2 Introduction
- 24.3 64-Pin Plastic Quad Flat Pack (QFP)
Section 25. Ordering Information
- 25.1 Contents
- 25.2 Introduction
- 25.3 MC Order Numbers

M68HC08

Microcontrollers

freescale.com

MC68HC908AB32

Technical Data

Rev. 1.1

MC68HC908AB32/D

August 2, 2005

Summary of content (392 pages)

PAGE 1
MC68HC908AB32 Technical Data M68HC08 Microcontrollers Rev. 1.1 MC68HC908AB32/D August 2, 2005 freescale.
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Technical Data — MC68HC908AB32 List of Sections Section 1. General Description . . . . . . . . . . . . . . . . . . . . 29 Section 2. Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Section 3. Random-Access Memory (RAM) . . . . . . . . . . 57 Section 4. FLASH Memory . . . . . . . . . . . . . . . . . . . . . . . . 59 Section 5. EEPROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Section 6. Configuration Register (CONFIG) . . . . . . . . . 85 Section 7.
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List of Sections Section 20. Computer Operating Properly (COP) . . . . 353 Section 21. Low-Voltage Inhibit (LVI) . . . . . . . . . . . . . . 359 Section 22. Break Module (BRK) . . . . . . . . . . . . . . . . . . 365 Section 23. Electrical Specifications. . . . . . . . . . . . . . . 373 Section 24. Mechanical Specifications . . . . . . . . . . . . . 387 Section 25. Ordering Information . . . . . . . . . . . . . . . . . 389 Technical Data 4 MC68HC908AB32 — Rev. 1.
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Technical Data — MC68HC908AB32 Table of Contents Section 1. General Description 1.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 1.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 1.4 MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 1.5 Pin Assignments . . . . . .
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Table of Contents Section 2. Memory Map 2.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 2.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 2.3 Unimplemented Memory Locations . . . . . . . . . . . . . . . . . . . . . 41 2.4 Reserved Memory Locations . . . . . . . . . . . . . . . . . . . . . . . . . . 42 2.5 Input/Output (I/O) Section. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Table of Contents 5.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 5.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 5.5 EEPROM Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 5.6 EEPROM Timebase Requirements . . . . . . . . . . . . . . . . . . . . . 72 5.7 EEPROM Security Options. . . . . . . . . . . . . . . . . . . . . . . . . . . .72 5.8 EEPROM Block Protection . . . . . .
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Table of Contents 7.4 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 7.4.1 Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 7.4.2 Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 7.4.3 Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 7.4.4 Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 7.4.
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Table of Contents 8.6 Exception Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118 8.6.1 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 8.6.1.1 Hardware Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 8.6.1.2 SWI Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 8.6.2 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 8.6.3 Break Interrupts . .
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Table of Contents 9.5.5 9.5.6 9.5.7 9.5.8 Oscillator Enable Signal (SIMOSCEN). . . . . . . . . . . . . . . . 142 Crystal Output Frequency Signal (CGMXCLK) . . . . . . . . . 143 CGM Base Clock Output (CGMOUT). . . . . . . . . . . . . . . . . 143 CGM CPU Interrupt (CGMINT) . . . . . . . . . . . . . . . . . . . . . 143 9.6 CGM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 9.6.1 PLL Control Register (PCTL) . . . . . . . . . . . . . . . . . . . . . . . 144 9.6.
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Table of Contents Section 11. Timer Interface Module A (TIMA) 11.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .169 11.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 11.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 11.4 Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 11.5 Functional Description . . . . . . . . . . . .
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Table of Contents Section 12. Timer Interface Module B (TIMB) 12.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .195 12.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 12.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 12.4 Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 12.5 Functional Description . . . . . . . . . . . . .
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Table of Contents Section 13. Programmable Interrupt Timer (PIT) 13.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .221 13.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 13.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 13.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .222 13.4.1 PIT Counter Prescaler . . . . . . . . . . .
PAGE 14
Table of Contents 14.7.2 14.7.3 14.7.4 ADC Analog Ground Pin (AVSS/VREFL) . . . . . . . . . . . . . . . 234 ADC Voltage Reference High Pin (VREFH). . . . . . . . . . . . . 234 ADC Voltage In (VADIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 14.8 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 14.8.1 ADC Status and Control Register (ADSCR). . . . . . . . . . . . 235 14.8.2 ADC Data Register (ADR) . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 15
Table of Contents 15.6.2 15.7 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .259 SCI During Break Module Interrupts. . . . . . . . . . . . . . . . . . . .260 15.8 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 15.8.1 PTE0/TxD (Transmit Data). . . . . . . . . . . . . . . . . . . . . . . . . 260 15.8.2 PTE1/RxD (Receive Data) . . . . . . . . . . . . . . . . . . . . . . . . . 260 15.9 I/O Registers. . . . . . . . . . . . . .
PAGE 16
Table of Contents 16.10 Resetting the SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298 16.11 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299 16.11.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .299 16.11.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .299 16.12 SPI During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . 300 16.13 I/O Signals . . . .
PAGE 17
Table of Contents 17.7 Port E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326 17.7.1 Port E Data Register (PTE) . . . . . . . . . . . . . . . . . . . . . . . . 326 17.7.2 Data Direction Register E (DDRE) . . . . . . . . . . . . . . . . . . . 328 17.8 Port F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329 17.8.1 Port F Data Register (PTF) . . . . . . . . . . . . . . . . . . . . . . . . 329 17.8.
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Table of Contents 19.5.3 Keyboard Interrupt Enable Register . . . . . . . . . . . . . . . . . . 351 19.6 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351 19.7 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351 19.8 Keyboard Module During Break Interrupts . . . . . . . . . . . . . . . 352 Section 20. Computer Operating Properly (COP) 20.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 19
Table of Contents 21.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .360 21.4.1 Polled LVI Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361 21.4.2 Forced Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . .361 21.4.3 False Reset Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361 21.5 LVI Status Register (LVISR) . . . . . . . . . . . . . . . . . . . . . . . . . . 362 21.6 LVI Interrupts . . . . . . . . . . . .
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Table of Contents 23.4 Functional Operating Range. . . . . . . . . . . . . . . . . . . . . . . . . . 375 23.5 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375 23.6 5.0-V DC Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . 376 23.7 EEPROM and Memory Characteristics . . . . . . . . . . . . . . . . . 377 23.8 5.0-V Control Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378 23.9 Timer Interface Module Characteristics . . .
PAGE 21
Technical Data — MC68HC908AB32 List of Figures Figure Title 1-1 1-2 1-3 MC68HC908AB32 Block Diagram . . . . . . . . . . . . . . . . . . . . . . 32 64-Pin QFP Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Power Supply Bypassing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 2-1 2-2 Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Control, Status, and Data Registers . . . . . . . . . . . . . . . . . . . . .
PAGE 22
List of Figures Figure Title Page 8-1 8-2 8-3 8-4 8-5 8-6 8-7 8-8 8-9 8-10 8-11 8-12 8-13 8-14 8-15 8-16 8-17 8-18 8-19 SIM Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 SIM I/O Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . .112 CGM Clock Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 External Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114 Internal reset timing . . . . . . . . . . . . .
PAGE 23
List of Figures Figure Title Page 11-2 TIMA I/O Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . 173 11-3 PWM Period and Pulse Width . . . . . . . . . . . . . . . . . . . . . . . . 177 11-4 TIMA Status and Control Register (TASC) . . . . . . . . . . . . . . . 184 11-5 TIMA Counter Register High (TACNTH). . . . . . . . . . . . . . . . . 186 11-6 TIMA Counter Register Low (TACNTL) . . . . . . . . . . . . . . . . . 187 11-7 TIMA Counter Modulo Register High (TAMODH). . . . . . . . . .
PAGE 24
List of Figures Figure Title 12-16 12-17 12-18 12-19 12-20 12-21 TIMB Channel 1 Register High (TBCH1H) . . . . . . . . . . . . . . . 219 TIMB Channel 1 Register Low (TBCH1L). . . . . . . . . . . . . . . . 219 TIMB Channel 2 Register High (TBCH2H) . . . . . . . . . . . . . . . 219 TIMB Channel 2 Register Low (TBCH2L). . . . . . . . . . . . . . . . 219 TIMB Channel 3 Register High (TBCH3H) . . . . . . . . . . . . . . . 220 TIMB Channel 3 Register Low (TBCH3L). . . . . . . . . . . . . . . .
PAGE 25
List of Figures Figure Title 16-1 16-2 16-3 16-4 16-5 16-6 16-7 16-8 16-9 16-10 16-11 16-12 16-13 16-14 16-15 SPI I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . .281 SPI Module Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . .282 Full-Duplex Master-Slave Connections . . . . . . . . . . . . . . . . . 283 Transmission Format (CPHA = 0) . . . . . . . . . . . . . . . . . . . . . 287 CPHA/SS Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 26
List of Figures Figure 17-21 17-22 17-23 17-24 17-25 17-26 17-27 Title Page Port F Input Pullup Enable Register (PTFPUE) . . . . . . . . . . . 332 Port G Data Register (PTG) . . . . . . . . . . . . . . . . . . . . . . . . . . 333 Data Direction Register G (DDRG). . . . . . . . . . . . . . . . . . . . . 333 Port G I/O Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334 Port H Data Register (PTH) . . . . . . . . . . . . . . . . . . . . . . . . . .
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Technical Data — MC68HC908AB32 List of Tables Table Title Page 1-1 1-2 1-3 I/O Pins Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 Signal Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Clock Source Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 2-1 Vector Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 5-1 5-2 EEPROM Array Address Blocks. . . . . . . . . . . . . . . . . . . . . .
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List of Tables Table Title Page 12-1 Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 12-2 Prescaler Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 12-3 Mode, Edge, and Level Selection . . . . . . . . . . . . . . . . . . . . . . 217 13-1 PIT Prescaler Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 14-1 Mux Channel Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Technical Data — MC68HC908AB32 Section 1. General Description 1.1 Contents 1.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 1.4 MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 1.5 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 1.6 Pin Functions . . . . . . . . . . . .
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General Description 1.2 Introduction The MC68HC908AB32 is a member of the low-cost, high-performance M68HC08 Family of 8-bit microcontroller units (MCUs) with embedded EEPROM for user data storage. All MCUs in the family use the enhanced M68HC08 central processor unit (CPU08) and are available with a variety of modules, memory sizes and types, and package types. 1.
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General Description • 51 general-purpose input/output (I/O) pins: – 30 shared-function I/O pins – 5-bit keyboard wakeup port – Selectable pullups on inputs on port D and port F • System protection features – Optional computer operating properly (COP) reset – Low-voltage detection with optional reset – Illegal opcode detection with optional reset – Illegal address detection with optional reset • 64-pin quad flat pack (QFP) Features of the CPU08 include the following: • Enhanced HC05 programming model
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DDRA PORTA PORTB PTB7/ATD7 – PTB0/ATD0 PORTC PORTD PROGRAMMABLE INTERRUPT TIMER MODULE DDRB 4-CHANNEL TIMER INTERFACE MODULE B DDRC CONTROL AND STATUS REGISTERS — 80 BYTES PTA7 – PTA0 DDRD 4-CHANNEL TIMER INTERFACE MODULE A DDRE ARITHMETIC/LOGIC UNIT (ALU) PORTE CPU REGISTERS USER FLASH — 32,256 BYTES SERIAL COMMUNICATIONS INTERFACE MODULE MONITOR ROM — 307 BYTES SERIAL PERIPHERAL INTERFACE MODULE * RST * IRQ Freescale Semiconductor MC68HC908AB32 — Rev. 1.
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General Description 1.5 Pin Assignments PTC1 PTC0 OSC1 OSC2 CGMXFC VSSA VDDA VREFH PTD7 PTD6/TACLK PTD5 PTD4/TBCLK 61 60 59 58 57 56 55 54 53 52 51 50 PTH1/KBD4 PTC2/MCLK 62 PTC4 49 PTC3 63 64 PTC5 Figure 1-2 shows the pin assignment for the MC68HC908AB32.
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General Description 1.6 Pin Functions Description of pin functions are provided here. 1.6.1 Power Supply Pins (VDD and VSS) VDD and VSS are the power supply and ground pins. The MCU operates from a single power supply. Fast signal transitions on MCU pins place high, short-duration current demands on the power supply. To prevent noise problems, take special care to provide power supply bypassing at the MCU as Figure 1-3 shows. Place the C1 bypass capacitor as close to the MCU as possible.
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General Description 1.6.2 Oscillator Pins (OSC1 and OSC2) The OSC1 and OSC2 pins are the connections for the on-chip oscillator circuit. See Section 9. Clock Generator Module (CGM). 1.6.3 External Reset Pin (RST) A logic 0 on the RST pin forces the MCU to a known start-up state. RST is bidirectional, allowing a reset of the entire system. It is driven low when any internal reset source is asserted. This pin contains an internal pullup resistor. See Section 8. System Integration Module (SIM). 1.6.
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General Description 1.6.8 ADC Voltage Reference Pin (VREFH) VREFH is the power supply for setting the reference voltage VREFH. Connect this pin to a voltage such that 1.5V < VREFH ≤ VDDAREF. 1.6.9 Analog Supply Pin (VDDAREF) The VDDAREF analog supply pin is used only for the supply connections for the analog-to-digital convertor (ADC). 1.6.10 External Filter Capacitor Pin (CGMXFC) CGMXFC is an external filter capacitor connection for the CGM. See Section 9. Clock Generator Module (CGM). 1.6.
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General Description 1.6.14 Port D I/O Pins (PTD7–PTD0) PTD7–PTD0 are general-purpose bidirectional I/O port pins. PTD6 and PTD4 are special function port pins that are shared with the timer interface modules (TIMA and TIMB). See Section 11. Timer Interface Module A (TIMA) and Section 12. Timer Interface Module B (TIMB). 1.6.15 Port E I/O Pins (PTE7/SPSCK–PTE0/TxD) PTE7–PTE0 are special function, bidirectional port pins.
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General Description 1.7 I/O Pin Summary Table 1-1.
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General Description Table 1-1.
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General Description 1.8 Signal Name Conventions Table 1-2. Signal Name Conventions Signal name Description CGMXCLK Buffered version of OSC1 from clock generator module (CGM) CGMOUT PLL-based or OSC1-based clock output from CGM module) Bus clock CGMOUT divided by two SPSCK SPI serial clock (see 16.13.3 SPSCK (Serial Clock)) TACLK External clock input for TIMA (see 11.9.1 TIMA Clock Pin) TBCLK External clock input for TIMB (see 12.9.1 TIMB Clock Pin) 1.9 Clock Source Summary Table 1-3.
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Technical Data — MC68HC908AB32 Section 2. Memory Map 2.1 Contents 2.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 2.3 Unimplemented Memory Locations . . . . . . . . . . . . . . . . . . . . . 41 2.4 Reserved Memory Locations . . . . . . . . . . . . . . . . . . . . . . . . . . 42 2.5 Input/Output (I/O) Section. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 2.2 Introduction The CPU08 can address 64K-bytes of memory space.
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Memory Map 2.4 Reserved Memory Locations Accessing a reserved location can have unpredictable effects on MCU operation. In the Figure 2-1 and in register figures in this document, reserved locations are marked with the word Reserved or with the letter R. 2.5 Input/Output (I/O) Section Most of the control, status, and data registers are in the zero page $0000–$004F.
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Memory Map $0000 I/O Registers 80 Bytes ↓ $004F $0050 RAM 1,024 Bytes ↓ $044F $0450 Unimplemented 176 Bytes ↓ $04FF $0500 Reserved 128 Bytes ↓ $057F $0580 Unimplemented 640 Bytes ↓ $07FF $0800 EEPROM 512 Bytes ↓ $09FF $0A00 Unimplemented 30,208 Bytes ↓ $7FFF $8000 FLASH Memory 32,256 Bytes ↓ $FDFF $FE00 SIM Break Status Register (SBSR) $FE01 SIM Reset Status Register (SRSR) $FE02 Reserved $FE03 SIM Break Flag Control Register (SBFCR) $FE04 ↓ $FE07 Reserved 4 Bytes $FE08 FLASH Cont
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Memory Map $FE09 ↓ $FE0B Reserved 3 Bytes $FE0C Break Address Register High (BRKH) $FE0D Break Address Register Low (BRKL) $FE0E Break Status and Control Register (BRKSCR) $FE0F LVI Status Register (LVISR) $FE10 EEPROM Divider Non-volatile Register High (EEDIVHNVR) $FE11 EEPROM Divider Non-volatile Register Low (EEDIVLNVR) $FE12 ↓ $FE19 Reserved 8 Bytes $FE1A EEPROM Timebase Divider Register High (EEDIVH) $FE1B EEPROM Timebase Divider Register Low (EEDIVL) $FE1C EEPROM Non-volatile Regi
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Memory Map Addr.
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Memory Map Addr.
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Memory Map Addr.
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Memory Map Addr.
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Memory Map Addr.
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Memory Map Addr.
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Memory Map Addr.
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Memory Map Addr.
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Memory Map Addr.
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Memory Map Addr.
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Memory Map Addr.
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Memory Map Table 2-1.
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Technical Data — MC68HC908AB32 Section 3. Random-Access Memory (RAM) 3.1 Contents 3.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 3.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 3.2 Introduction This section describes the 1024 bytes of RAM (random-access memory). 3.3 Functional Description Addresses $0050 through $044F are RAM locations. The location of the stack RAM is programmable.
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Random-Access Memory (RAM) During a subroutine call, the CPU uses two bytes of the stack to store the return address. The stack pointer decrements during pushes and increments during pulls. NOTE: Be careful when using nested subroutines. The CPU may overwrite data in the RAM during a subroutine or during the interrupt stacking operation. Technical Data 58 MC68HC908AB32 — Rev. 1.
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Technical Data — MC68HC908AB32 Section 4. FLASH Memory 4.1 Contents 4.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 4.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 4.4 FLASH Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 4.5 FLASH Page Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . 61 4.6 FLASH Mass Erase Operation . . . . . . . . . . . . . . . . . . .
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FLASH Memory page. Hence the minimum erase page size is 128 bytes. Program and erase operations are facilitated through control bits in the FLASH Control Register (FLCR). Details for these operations appear later in this section. The address ranges for the user memory and vectors are: • $8000–$FDFF; user memory. • $FF7E; FLASH block protect register. • $FE08; FLASH control register. • $FFDC–$FFFF; these locations are reserved for user-defined interrupt and reset vectors.
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FLASH Memory MASS — Mass Erase Control Bit Setting this read/write bit configures the 32K-byte FLASH array for mass erase operation. 1 = MASS erase operation selected 0 = MASS erase operation unselected ERASE — Erase Control Bit This read/write bit configures the memory for erase operation. ERASE is interlocked with the PGM bit such that both bits cannot be equal to 1 or set to 1 at the same time.
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FLASH Memory 9. Clear the HVEN bit. 10. After a time, trcv (typ. 1µs), the memory can be accessed again in read mode. NOTE: While these operations must be performed in the order shown, other unrelated operations may occur between the steps. 4.6 FLASH Mass Erase Operation Use this step-by-step procedure to erase entire FLASH memory to read as logic 1: 1. Set both the ERASE bit, and the MASS bit in the FLASH control register. 2. Read from the FLASH block protect register. 3.
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FLASH Memory 4.7 FLASH Program/Read Operation Programming of the FLASH memory is done on a row basis. A row consists of 64 consecutive bytes starting from addresses $XX00, $XX40, $0080 and $XXC0. Use this step-by-step procedure to program a row of FLASH memory (Figure 4-2 is a flowchart representation): NOTE: In order to avoid program disturbs, the row must be erased before any byte on that row is programmed. 1. Set the PGM bit.
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FLASH Memory NOTE: Programming and erasing of FLASH locations cannot be performed by code being executed from the FLASH memory. While these operations must be performed in the order shown, other unrelated operations may occur between the steps. Do not exceed tPROG maximum. See 23.13 FLASH Memory Characteristics. 4.
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FLASH Memory Algorithm for programming a row (64 bytes) of FLASH memory 1 Set PGM bit 2 Read the FLASH block protect register 3 Write any data to any FLASH address within the row address range desired 4 Wait for a time, tnvs 5 Set HVEN bit 6 Wait for a time, tpgs 7 Write data to the FLASH address to be programmed 8 Wait for a time, tPROG Completed programming this row? Y N NOTE: The time between each FLASH address change (step 7 to step 7), or the time between the last FLASH address pro
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FLASH Memory 4.8.1 FLASH Block Protect Register The FLASH block protect register (FLBPR) is implemented as a byte within the FLASH memory, and therefore can only be written during a programming sequence of the FLASH memory. The value in this register determines the starting location of the protected range within the FLASH memory. Address: Read: Write: Reset: $FF7E Bit 7 6 5 4 3 2 1 Bit 0 BPR7 BPR6 BPR5 BPR4 BPR3 BPR2 BPR1 BPR0 U U U U U U U U U = Unaffected by reset.
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FLASH Memory Examples of protect start address: BPR[7:0] Start of Address of Protect Range $00 The entire FLASH memory is protected. $01 (0000 0001) $8080 (1000 0000 1000 0000) $02 (0000 0010) $8100 (1000 0001 0000 0000) and so on... $FE (1111 1110) $FF00 (1111 1111 0000 0000) $FF The entire FLASH memory is not protected. Note: The end address of the protected range is always $FFFF. 4.
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FLASH Memory Technical Data 68 MC68HC908AB32 — Rev. 1.
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Technical Data — MC68HC908AB32 Section 5. EEPROM 5.1 Contents 5.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 5.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 5.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 5.5 EEPROM Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 5.6 EEPROM Timebase Requirements . . . . . . . . . . . . . .
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EEPROM 5.3 Features Features of the EEPROM include the following: Addr.
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EEPROM $FE1F Read: EEPROM Array Configuration Register Write: (EEACR) Reset: CON3 CON2 CON1 EEPRTCT EEBP3 EEBP2 EEBP1 EEBP0 Contents of EENVR ($FE1C) * Non-volatile EEPROM register; write by programming. = Unimplemented R = Reserved Figure 5-1. EEPROM I/O Register Summary 5.4 Functional Description The 512 bytes of EEPROM is located at $0800–$09FF, and can be programmed or erased without an additional external high voltage supply.
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EEPROM For the EEDIVNVR (two 8-bit registers: EEDIVHNVR and EEDIVLNVR), the corresponding volatile register is the EEPROM timebase divider register (EEDIV: EEDIVH and EEDIVL) Technical Data 72 MC68HC908AB32 — Rev. 1.
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EEPROM 5.6 EEPROM Timebase Requirements A 35µs timebase is required by the EEPROM control circuit for program and erase of EEPROM content. This timebase is derived from dividing the CGMXCLK or bus clock (selected by EEDIVCLK bit in CONFIG2 register) using a timebase divider circuit, controlled by the 16-bit EEPROM timebase divider register (EEDIVH and EEDIVL). As the CGMXCLK or bus clock is user selected, the EEPROM timebase divider register must be configured with the appropriate value to obtain the 35µs.
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EEPROM Table 5-1. EEPROM Array Address Blocks Block Number (EEBPx) Address Range EEBP0 $0800–$087F EEBP1 $0880–$08FF EEBP2 $0900–$097F EEBP3 $0980–$09FF These bits are effective after a reset or a read to EENVR register. The block protect configuration can be modified by erasing/programming the corresponding bits in the EENVR register and then reading the EENVR register. 5.9 EEPROM Programming and Erasing The unprogrammed or erased state of an EEPROM bit is a logic 1.
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EEPROM 5.9.1 EEPROM Programming The unprogrammed or erased state of an EEPROM bit is a logic 1. Programming changes the state to a logic 0. Only EEPROM bytes in the non-protected blocks and the EENVR register can be programmed. Use the following procedure to program a byte of EEPROM: 1. Clear EERAS1 and EERAS0, and set EELAT in the EECR.(A) 2. Write the desired data to the desired EEPROM address.(B) 3. Set the EEPGM bit.(C) Go to step 7 if AUTO is set. 4. Wait for a time, tEEPGM, to program the byte. 5.
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EEPROM D. The delay time for the EEPGM bit to be cleared in AUTO mode is less than tEEPGM. However, on other MCUs, this delay time may be different. For forward compatibility, software should not make any dependency on this delay time. E. Any attempt to clear both EEPGM and EELAT bits with a single instruction will only clear EEPGM. This is to allow time for removal of high voltage from the EEPROM array. 5.9.2 EEPROM Erasing The programmed state of an EEPROM bit is logic 0.
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EEPROM NOTE: A. Setting the EELAT bit configures the address and data buses to latch data for erasing the array. Only valid EEPROM addresses will be latched. If EELAT is set, other writes to the EECR will be allowed after a valid EEPROM write. B. If more than one valid EEPROM writes occur, the last address and data will be latched, overriding the previous address and data. Once written data to the desired address, do not read EEPROM locations other than the written location.
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EEPROM 5.10.2 Stop Mode The STOP instruction reduces the EEPROM power consumption to a minimum. The STOP instruction should not be executed while the programming and erasing sequence is in progress. If stop mode is entered while EELAT and EEPGM is set, the programming sequence will be stopped and the programming voltage to the EEPROM array removed. The programming sequence will be restarted after leaving stop mode; access to the EEPROM is only possible after the programming sequence has completed.
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EEPROM EEOFF — EEPROM Power-Off This read/write bit disables the EEPROM module for lower power consumption. Any attempts to access the array will give unpredictable results. Reset clears this bit. 1 = Disable EEPROM array 0 = Enable EEPROM array EERAS[1:0] — Erase/Program Mode Select Bits These read/write bits set the erase modes. Reset clears these bits. Table 5-2.
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EEPROM EEPGM — EEPROM Program/Erase Enable This read/write bit enables the internal charge pump and applies the programming/erasing voltage to the EEPROM array if the EELAT bit is set and a write to a valid EEPROM location has occurred. Reset clears the EEPGM bit. 1 = EEPROM programming/erasing power switched on 0 = EEPROM programming/erasing power switched off NOTE: Writing 0s to both the EELAT and EEPGM bits with a single instruction will only clear EEPGM.
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EEPROM EEBP[3:0] — EEPROM Block Protection Bits These bits prevent blocks of EEPROM array from being programmed or erased. 1 = EEPROM array block is protected 0 = EEPROM array block is unprotected Block Number (EEBPx) Address Range EEBP0 $0800–$087F EEBP1 $0880–$08FF EEBP2 $0900–$097F EEBP3 $0980–$09FF 5.11.2.1 EEPROM Non-Volatile Register The contents of this register is loaded into the EEPROM array configuration register (EEACR) after a reset.
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EEPROM These two read/write registers are respectively loaded with the contents of the EEPROM timebase divider non-volatile registers (EEDIVHNVR and EEDIVLNVR) after a reset. Address: $FE1A Bit 7 6 5 4 3 2 1 Bit 0 EEDIVSECD R R R R EEDIV10 EEDIV9 EEDIV8 Read: Write: Reset: Contents of EEDIVHNVR ($FE10) Figure 5-5.
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EEPROM The EEDIV value is calculated by the following formula: EEDIV = INT [ Reference frequency (Hz) × 35 × 10 –6 + 0.5 ] Where the result inside the bracket is rounded down to the nearest integer value. For example, if the reference frequency is 4.9152MHz, the EEDIV value is 172. NOTE: Programming/erasing the EEPROM with an improper EEDIV value may result in data lost and reduce endurance of the EEPROM device. 5.11.3.
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EEPROM These two registers are protected from erase and program operations if the EEDIVSECD is set to logic 1 in the EEDIVH (see 5.11.3 EEPROM Timebase Divider Register), or programmed to a logic 1 in the EEDIVHNVR. NOTE: Once EEDIVSECD in the EEDIVHNVR is programmed to 0 and after a system reset, the EEDIV security feature is permanently enabled because the EEDIVSECD bit in the EEDIVH is always loaded with a 0 thereafter.
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Technical Data — MC68HC908AB32 Section 6. Configuration Register (CONFIG) 6.1 Contents 6.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 6.3 Functional description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 6.4 Configuration Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 6.5 Configuration Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 6.
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Configuration Register (CONFIG) 6.3 Functional description The configuration registers are used in the initialization of various options. The configuration registers can be written once after each reset. All of the configuration register bits are cleared during reset. Since the various options affect the operation of the MCU, it is recommended that these registers be written immediately after reset. The configuration registers are located at $001F and $003F.
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Configuration Register (CONFIG) LVIPWRD — LVI Power Disable Bit LVIPWRD disables the LVI module. (See Section 21. Low-Voltage Inhibit (LVI).) 1 = LVI module power disabled 0 = LVI module power enabled SSREC — Short Stop Recovery Bit SSREC enables the CPU to exit stop mode with a delay of 32 CGMXCLK cycles instead of a 4096 CGMXCLK cycle delay.
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Configuration Register (CONFIG) 6.5 Configuration Register 2 Address: Read: Write: $003F Bit 7 6 5 4 3 2 1 Bit 0 R EEDIVCLK R R R R R R Reset: 0 R = Reserved Figure 6-2. Configuration Register 2 (CONFIG2) EEDIVCLK — EEPROM Timebase Divider Clock Select Bit EEDIVCLK selects the reference clock source for the EEPROM timebase divider. (See Section 5. EEPROM.
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Technical Data — MC68HC908AB32 Section 7. Central Processor Unit (CPU) 7.1 Contents 7.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 7.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 7.4 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 7.4.1 Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 7.4.2 Index Register . . . . . .
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Central Processor Unit (CPU) 7.
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Central Processor Unit (CPU) 7 0 ACCUMULATOR (A) 15 0 H X INDEX REGISTER (H:X) 0 15 STACK POINTER (SP) 0 15 PROGRAM COUNTER (PC) 7 0 V 1 1 H I N Z C CONDITION CODE REGISTER (CCR) CARRY/BORROW FLAG ZERO FLAG NEGATIVE FLAG INTERRUPT MASK HALF-CARRY FLAG TWO’S COMPLEMENT OVERFLOW FLAG Figure 7-1. CPU Registers 7.4.1 Accumulator The accumulator is a general-purpose 8-bit register. The CPU uses the accumulator to hold operands and the results of arithmetic/logic operations.
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Central Processor Unit (CPU) 7.4.2 Index Register The 16-bit index register allows indexed addressing of a 64K-byte memory space. H is the upper byte of the index register, and X is the lower byte. H:X is the concatenated 16-bit index register. In the indexed addressing modes, the CPU uses the contents of the index register to determine the conditional address of the operand. The index register can serve also as a temporary data storage location.
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Central Processor Unit (CPU) Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Read: Write: Reset: Figure 7-4. Stack Pointer (SP) NOTE: The location of the stack is arbitrary and may be relocated anywhere in RAM. Moving the SP out of page 0 ($0000 to $00FF) frees direct address (page 0) space. For correct operation, the stack pointer must point only to RAM locations. 7.4.
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Central Processor Unit (CPU) 5 are set permanently to logic 1. The following paragraphs describe the functions of the condition code register. Read: Write: Reset: Bit 7 6 5 4 3 2 1 Bit 0 V 1 1 H I N Z C X 1 1 X 1 X X X X = Indeterminate Figure 7-6. Condition Code Register (CCR) V — Overflow Flag The CPU sets the overflow flag when a two's complement overflow occurs. The signed branch instructions BGT, BGE, BLE, and BLT use the overflow flag.
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Central Processor Unit (CPU) I — Interrupt Mask When the interrupt mask is set, all maskable CPU interrupts are disabled. CPU interrupts are enabled when the interrupt mask is cleared. When a CPU interrupt occurs, the interrupt mask is set automatically after the CPU registers are saved on the stack, but before the interrupt vector is fetched. 1 = Interrupts disabled 0 = Interrupts enabled NOTE: To maintain M6805 Family compatibility, the upper byte of the index register (H) is not stacked automatically.
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Central Processor Unit (CPU) C — Carry/Borrow Flag The CPU sets the carry/borrow flag when an addition operation produces a carry out of bit 7 of the accumulator or when a subtraction operation requires a borrow. Some instructions — such as bit test and branch, shift, and rotate — also clear or set the carry/borrow flag. 1 = Carry out of bit 7 0 = No carry out of bit 7 7.5 Arithmetic/Logic Unit (ALU) The ALU performs the arithmetic and logic operations defined by the instruction set.
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Central Processor Unit (CPU) 7.6.2 Stop Mode The STOP instruction: • Clears the interrupt mask (I bit) in the condition code register, enabling external interrupts. After exit from stop mode by external interrupt, the I bit remains clear. After exit by reset, the I bit is set. • Disables the CPU clock After exiting stop mode, the CPU clock begins running after the oscillator stabilization delay. 7.
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Central Processor Unit (CPU) V H I N Z C ADC #opr ADC opr ADC opr ADC opr,X ADC opr,X ADC ,X ADC opr,SP ADC opr,SP A ← (A) + (M) + (C) Add with Carry ↕ ↕ IMM DIR EXT IX2 – ↕ ↕ ↕ IX1 IX SP1 SP2 A9 B9 C9 D9 E9 F9 9EE9 9ED9 ii dd hh ll ee ff ff IMM DIR EXT IX2 – ↕ ↕ ↕ IX1 IX SP1 SP2 AB BB CB DB EB FB 9EEB 9EDB ii dd hh ll ee ff ff ADD #opr ADD opr ADD opr ADD opr,X ADD opr,X ADD ,X ADD opr,SP ADD opr,SP Add without Carry AIS #opr Add Immediate Value (Signed) to SP SP ← (SP) + (16 « M) – – – – –
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Central Processor Unit (CPU) Effect on CCR V H I N Z C Cycles Description Operand Operation Opcode Source Form Address Mode Table 7-1.
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Central Processor Unit (CPU) Table 7-1.
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Central Processor Unit (CPU) V H I N Z C CMP #opr CMP opr CMP opr CMP opr,X CMP opr,X CMP ,X CMP opr,SP CMP opr,SP Compare A with M (A) – (M) COM opr COMA COMX COM opr,X COM ,X COM opr,SP Complement (One’s Complement) CPHX #opr CPHX opr Compare H:X with M CPX #opr CPX opr CPX opr CPX ,X CPX opr,X CPX opr,X CPX opr,SP CPX opr,SP Compare X with M DAA Decimal Adjust A (H:X) – (M:M + 1) (X) – (M) (A)10 DBNZ opr,rel DBNZA rel Decrement and Branch if Not Zero DBNZX rel DBNZ opr,X,rel DBNZ X,rel DBN
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Central Processor Unit (CPU) V H I N Z C EOR #opr EOR opr EOR opr EOR opr,X EOR opr,X EOR ,X EOR opr,SP EOR opr,SP INC opr INCA INCX INC opr,X INC ,X INC opr,SP JMP opr JMP opr JMP opr,X JMP opr,X JMP ,X JSR opr JSR opr JSR opr,X JSR opr,X JSR ,X Load A from M LDHX #opr LDHX opr Load H:X from M LSL opr LSLA LSLX LSL opr,X LSL ,X LSL opr,SP DIR INH INH – IX1 IX SP1 3C 4C 5C 6C 7C 9E6C dd ff ee ff ff ff 2 3 4 4 3 2 4 5 4 1 1 4 3 5 PC ← Jump Address dd hh ll ee ff ff 2 3 4 3 2 PC ← (PC) + n (n =
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Central Processor Unit (CPU) V H I N Z C LSR opr LSRA LSRX LSR opr,X LSR ,X LSR opr,SP Logical Shift Right 0 C b7 MOV opr,opr MOV opr,X+ MOV #opr,opr MOV X+,opr Move MUL Unsigned multiply ↕ b0 DIR INH INH – – 0 ↕ ↕ IX1 IX SP1 (M)Destination ← (M)Source 0 – – ↕ ↕ H:X ← (H:X) + 1 (IX+D, DIX+) X:A ← (X) × (A) DD DIX+ – IMD IX+D – 0 – – – 0 INH DIR INH INH – – ↕ ↕ ↕ IX1 IX SP1 34 44 54 64 74 9E64 4E 5E 6E 7E dd ff 4 1 1 4 3 5 dd dd dd ii dd dd 5 4 4 4 ff 42 30 40 50 60 70 9E60 Cycles Eff
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Central Processor Unit (CPU) V H I N Z C DIR INH INH – – ↕ ↕ ↕ IX1 IX SP1 36 46 56 66 76 9E66 dd Cycles Effect on CCR Description Operand Operation Opcode Source Form Address Mode Table 7-1.
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Central Processor Unit (CPU) V H I N Z C SUB #opr SUB opr SUB opr SUB opr,X SUB opr,X SUB ,X SUB opr,SP SUB opr,SP Subtract A ← (A) – (M) ↕ IMM DIR EXT IX2 – – ↕ ↕ ↕ IX1 IX SP1 SP2 A0 B0 C0 D0 E0 F0 9EE0 9ED0 ii dd hh ll ee ff ff ff ee ff Cycles Effect on CCR Description Operand Operation Opcode Source Form Address Mode Table 7-1.
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Central Processor Unit (CPU) V H I N Z C A C CCR dd dd rr DD DIR DIX+ ee ff EXT ff H H hh ll I ii IMD IMM INH IX IX+ IX+D IX1 IX1+ IX2 M N Accumulator Carry/borrow bit Condition code register Direct address of operand Direct address of operand and relative offset of branch instruction Direct to direct addressing mode Direct addressing mode Direct to indexed with post increment addressing mode High and low bytes of offset in indexed, 16-bit offset addressing Extended addressing mode Offset byte in indexed,
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MC68HC908AB32 — Rev. 1.1 Freescale Semiconductor Table 7-2.
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Central Processor Unit (CPU) Technical Data 108 MC68HC908AB32 — Rev. 1.
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Technical Data — MC68HC908AB32 Section 8. System Integration Module (SIM) 8.1 Contents 8.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 8.3 SIM Bus Clock Control and Generation . . . . . . . . . . . . . . . . . 112 8.3.1 Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 8.3.2 Clock Start-Up from POR or LVI Reset . . . . . . . . . . . . . . . 113 8.3.3 Clocks in Stop and Wait Modes . . . . . . . . . . . . . . . . . .
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System Integration Module (SIM) 8.8 SIM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 8.8.1 SIM Break Status Register . . . . . . . . . . . . . . . . . . . . . . . . . 127 8.8.2 SIM Reset Status Register . . . . . . . . . . . . . . . . . . . . . . . . . 128 8.8.3 SIM Break Flag Control Register . . . . . . . . . . . . . . . . . . . . 129 8.
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System Integration Module (SIM) MODULE STOP MODULE WAIT CPU STOP (FROM CPU) CPU WAIT (FROM CPU) STOP/WAIT CONTROL SIMOSCEN (TO CGM) SIM COUNTER COP CLOCK CGMXCLK (FROM CGM) CGMOUT (FROM CGM) ÷2 CLOCK CONTROL RESET PIN LOGIC CLOCK GENERATORS INTERNAL CLOCKS LVI (FROM LVI MODULE) POR CONTROL MASTER RESET CONTROL RESET PIN CONTROL SIM RESET STATUS REGISTER ILLEGAL OPCODE (FROM CPU) ILLEGAL ADDRESS (FROM ADDRESS MAP DECODERS) COP (FROM COP MODULE) RESET INTERRUPT SOURCES INTERRUPT CONTROL AND P
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System Integration Module (SIM) Addr. Register Name Bit 7 6 5 4 3 2 R R R R R R 0 0 0 0 0 0 0 0 POR PIN COP ILOP ILAD 0 LVI 0 1 0 0 0 0 0 0 0 BCFE R R R R R R R Read: SIM Break Status Register $FE00 Write: (SBSR) Reset: 1 SBSW Note Bit 0 R Note: Writing a logic 0 clears SBSW. Read: SIM Reset Status Register $FE01 Write: (SRSR) POR: $FE03 Read: SIM Break Flag Control Register Write: (SBFCR) Reset: 0 = Unimplemented R = Reserved Figure 8-2.
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System Integration Module (SIM) 8.3.1 Bus Timing In user mode, the internal bus frequency is either the crystal oscillator output (CGMXCLK) divided by four or the PLL output (CGMVCLK) divided by four. See Section 9. Clock Generator Module (CGM). 8.3.
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System Integration Module (SIM) All of these resets produce the vector $FFFE–FFFF ($FEFE–FEFF in monitor mode) and assert the internal reset signal (IRST). IRST causes all registers to be returned to their default values and all modules to be returned to their reset states. An internal reset clears the SIM counter (see 8.5 SIM Counter), but an external reset does not. Each of the resets sets a corresponding bit in the SIM reset status register (SRSR). (See 8.8 SIM Registers.) 8.4.
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System Integration Module (SIM) IRST RST RST PULLED LOW BY MCU 32 CYCLES 32 CYCLES CGMXCLK IAB VECTOR HIGH Figure 8-5. Internal reset timing The COP reset is asynchronous to the bus clock. ILLEGAL ADDRESS RST ILLEGAL OPCODE RST COPRST LVI POR INTERNAL RESET Figure 8-6. Sources of Internal Reset The active reset feature allows the part to issue a reset to peripherals and other chips within a system built around the MCU. 8.4.2.
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System Integration Module (SIM) • The RST pin is driven low during the oscillator stabilization time • The POR bit of the SIM reset status register (SRSR) is set and all other bits in the register are cleared OSC1 PORRST 4096 CYCLES 32 CYCLES 32 CYCLES CGMXCLK CGMOUT RST $FFFE IAB $FFFF Figure 8-7. POR Recovery 8.4.2.2 Computer Operating Properly (COP) Reset An input to the SIM is reserved for the COP reset signal.
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System Integration Module (SIM) 8.4.2.3 Illegal Opcode Reset The SIM decodes signals from the CPU to detect illegal instructions. An illegal instruction sets the ILOP bit in the SIM reset status register (SRSR) and causes a reset. If the STOP enable bit, STOP, in the configuration register 1 (CONFIG1) is logic 0, the SIM treats the STOP instruction as an illegal opcode and causes an illegal opcode reset. The SIM actively pulls down the RST pin for all internal reset sources. 8.4.2.
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System Integration Module (SIM) 8.5.1 SIM Counter during Power-On Reset The power-on reset (POR) module detects power applied to the MCU. At power-on, the POR circuit asserts the signal PORRST. Once the SIM is initialized, it enables the clock generation module (CGM) to drive the bus clock state machine. 8.5.2 SIM Counter during Stop Mode Recovery The SIM counter is also used for stop mode recovery. The STOP instruction clears the SIM counter.
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System Integration Module (SIM) 8.6.1 Interrupts At the beginning of an interrupt, the CPU saves the CPU register contents onto the stack and sets the interrupt mask (I-bit) to prevent additional interrupts. At the end of an interrupt, the RTI instruction recovers the CPU register contents from the stack so that normal processing can resume. Figure 8-8 shows interrupt entry timing, and Figure 8-9 shows interrupt recovery timing.
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System Integration Module (SIM) FROM RESET BREAK I BIT SET? INTERRUPT? YES NO YES I-BIT SET? NO IRQ INTERRUPT? YES NO STACK CPU REGISTERS SET I-BIT LOAD PC WITH INTERRUPT VECTOR AS MANY INTERRUPTS AS EXIST ON CHIP FETCH NEXT INSTRUCTION SWI INSTRUCTION? YES NO RTI INSTRUCTION? YES UNSTACK CPU REGISTERS NO EXECUTE INSTRUCTION Figure 8-10. Interrupt Processing 8.6.1.1 Hardware Interrupts Processing of a hardware interrupt begins after completion of the current instruction.
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System Integration Module (SIM) If more than one interrupt is pending at the end of an instruction execution, the highest priority interrupt is serviced first. Figure 8-11 demonstrates what happens when two interrupts are pending. If an interrupt is pending upon exit from the original interrupt service routine, the pending interrupt is serviced before the LDA instruction is executed.
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System Integration Module (SIM) Table 8-3.
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System Integration Module (SIM) 8.6.2 Reset All reset sources always have equal and highest priority and cannot be arbitrated. 8.6.3 Break Interrupts The break module can stop normal program flow at a softwareprogrammable break point by asserting its break interrupt output. See Section 22. Break Module (BRK). The SIM puts the CPU into the break state by forcing it to the SWI vector location. Refer to the break interrupt subsection of each module to see how each module is affected by the break state. 8.6.
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System Integration Module (SIM) 8.7 Low-Power Modes Executing the STOP or WAIT instruction puts the MCU in a low-powerconsumption mode for standby situations. The SIM holds the CPU in a non-clocked state. The operation of each of these modes is described below. Both STOP and WAIT clear the interrupt mask (I) in the condition code register, allowing interrupts to occur. 8.7.1 Wait Mode In wait mode, the CPU clocks are inactive while the peripheral clocks continue to run.
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System Integration Module (SIM) IAB $6E0B IDB $A6 $A6 $6E0C $A6 $00FF $01 $0B $00FE $00FD $00FC $6E EXITSTOPWAIT NOTE: EXITSTOPWAIT = RST pin OR CPU interrupt OR break interrupt Figure 8-13. Wait Recovery from Interrupt or Break 32 Cycles IAB IDB $6E0B $A6 $A6 32 Cycles RST VCT H RST VCT L $A6 RST CGMXCLK Figure 8-14. Wait Recovery from Internal Reset 8.7.2 Stop Mode In stop mode, the SIM counter is reset and the system clocks are disabled.
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System Integration Module (SIM) A break interrupt during stop mode sets the SIM break STOP/WAIT bit (SBSW) in the SIM break status register (SBSR). The SIM counter is held in reset from the execution of the STOP instruction until the beginning of stop recovery. It is then used to time the recovery period. Figure 8-15 shows stop mode entry timing.
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System Integration Module (SIM) 8.8 SIM Registers The SIM has three memory mapped registers. Table 8-4 shows the mapping of these registers. Table 8-4. SIM Registers Address Register Access Mode $FE00 SBSR User $FE01 SRSR User $FE03 SBFCR User 8.8.1 SIM Break Status Register The SIM break status register (SBSR) contains a flag to indicate that a break caused an exit from stop or wait mode.
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System Integration Module (SIM) ; This code works if the H register has been pushed onto the stack in the break ; service routine software. This code should be executed at the end of the ; break service routine software. HIBYTE EQU 5 LOBYTE EQU 6 ; If not SBSW, do RTI BRCLR SBSW,SBSR, RETURN ; See if STOP or WAIT mode was exited by ; break. TST LOBYTE,SP ; If RETURNLO is not 0, BNE DOLO ; then just decrement low byte. DEC HIBYTE,SP ; Else deal with high byte, too.
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System Integration Module (SIM) PIN — External Reset Bit 1 = Last reset caused by external reset pin (RST) 0 = POR or read of SRSR COP — Computer Operating Properly Reset Bit 1 = Last reset caused by COP counter 0 = POR or read of SRSR ILOP — Illegal Opcode Reset Bit 1 = Last reset caused by an illegal opcode 0 = POR or read of SRSR ILAD — Illegal Address Reset Bit (opcode fetches only) 1 = Last reset caused by an opcode fetch from an illegal address 0 = POR or read of SRSR LVI — Low-Voltage Inhibit Reset
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System Integration Module (SIM) Technical Data 130 MC68HC908AB32 — Rev. 1.
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Technical Data — MC68HC908AB32 Section 9. Clock Generator Module (CGM) 9.1 Contents 9.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 9.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 9.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133 9.4.1 Crystal Oscillator Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . .134 9.4.2 Phase-Locked Loop (PLL) Circuit . . .
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Clock Generator Module (CGM) 9.8.1 9.8.2 9.9 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151 CGM During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . 151 9.10 Acquisition/Lock Time Specifications . . . . . . . . . . . . . . . . . . . 151 9.10.1 Acquisition/Lock Time Definitions. . . . . . . . . . . . . . . . . . . .152 9.10.
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Clock Generator Module (CGM) 9.4 Functional Description The CGM consists of three major sub-modules: • Crystal oscillator circuit which generates the constant crystal frequency clock, CGMXCLK. • Phase-locked loop (PLL) which generates the programmable VCO frequency clock CGMVCLK. • Base clock selector circuit; this software-controlled circuit selects either CGMXCLK divided by two or the VCO clock CGMVCLK divided by two, as the base clock CGMOUT. The SIM derives the system clocks from CGMOUT.
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Clock Generator Module (CGM) Addr. $001C $001D $001E Register Name Bit 7 Read: PLL Control Register Write: (PCTL) Reset: Read: PLL Bandwidth Control Register Write: (PBWC) Reset: Read: PLL Programming Register Write: (PPG) Reset: PLLIE 0 AUTO 6 PLLF 0 LOCK 5 4 PLLON BCS 1 0 ACQ XLD 3 2 1 Bit 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 MUL7 MUL6 MUL5 MUL4 VRS7 VRS6 VRS5 VRS4 0 1 1 0 0 1 1 0 = Unimplemented Figure 9-2. CGM I/O Register Summary 9.4.
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Clock Generator Module (CGM) 9.4.2 Phase-Locked Loop (PLL) Circuit The PLL is a frequency generator that can operate in either acquisition mode or tracking mode, depending on the accuracy of the output frequency. The PLL can change between acquisition and tracking modes either automatically or manually. 9.4.2.
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Clock Generator Module (CGM) then slightly alters the DC voltage on the external capacitor connected to CGMXFC based on the width and direction of the correction pulse. The filter can make fast or slow corrections depending on its mode, described in 9.4.2.2 Acquisition and Tracking Modes. The value of the external capacitor and the reference frequency determines the speed of the corrections and the stability of the PLL.
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Clock Generator Module (CGM) In automatic bandwidth control mode (AUTO = 1), the lock detector automatically switches between acquisition and tracking modes. Automatic bandwidth control mode is used also to determine when the VCO clock, CGMVCLK, is safe to use as the source for the base clock, CGMOUT. See 9.6.2 PLL Bandwidth Control Register (PBWC). If PLL interrupts are enabled, the software can wait for a PLL interrupt request and then check the LOCK bit.
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Clock Generator Module (CGM) and require fast start-up. The following conditions apply when in manual mode: • ACQ is a writable control bit that controls the mode of the filter. Before turning on the PLL in manual mode, the ACQ bit must be clear. • Before entering tracking mode (ACQ = 1), software must wait a given time, tACQ (see 9.10 Acquisition/Lock Time Specifications), after turning on the PLL by setting PLLON in the PLL control register (PCTL).
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Clock Generator Module (CGM) 5. Calculate and verify the adequacy of the VCO and bus frequencies fVCLK and fBUS. f VCLK = N × f RCLK f BUS = ( f VCLK ) ⁄ 4 6. Select a VCO linear range multiplier, L. f VCLK L = round  ----------- f NOM  where fNOM = 4.9152MHz 7. Calculate and verify the adequacy of the VCO programmed center-of-range frequency fVRS. fVRS = (L)fNOM 8. Verify the choice of N and L by comparing fVCLK to fVRS and fVCLKDES.
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Clock Generator Module (CGM) • A zero value for N is interpreted exactly the same as a value of one. • A zero value for L disables the PLL and prevents its selection as the source for the base clock. (See 9.4.3 Base Clock Selector Circuit) 9.4.3 Base Clock Selector Circuit This circuit is used to select either the crystal clock, CGMXCLK, or the VCO clock, CGMVCLK, as the source of the base clock, CGMOUT.
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Clock Generator Module (CGM) • Crystal, X1 • Fixed capacitor, C1 • Tuning capacitor, C2 (can also be a fixed capacitor) • Feedback resistor, RB • Series resistor, RS (optional) The series resistor (RS) is included in the diagram to follow strict Pierce oscillator guidelines and may not be required for all ranges of operation, especially with high frequency crystals. Refer to the crystal manufacturer’s data for more information.
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Clock Generator Module (CGM) 9.5 I/O Signals The following paragraphs describe the CGM I/O signals. 9.5.1 Crystal Amplifier Input Pin (OSC1) The OSC1 pin is an input to the crystal oscillator amplifier. 9.5.2 Crystal Amplifier Output Pin (OSC2) The OSC2 pin is the output of the crystal oscillator inverting amplifier. 9.5.3 External Filter Capacitor Pin (CGMXFC) The CGMXFC pin is required by the loop filter to filter out phase corrections. A small external capacitor is connected to this pin.
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Clock Generator Module (CGM) 9.5.6 Crystal Output Frequency Signal (CGMXCLK) CGMXCLK is the crystal oscillator output signal. It runs at the full speed of the crystal (fXCLK) and is generated directly from the crystal oscillator circuit. Figure 9-3 shows only the logical relation of CGMXCLK to OSC1 and OSC2 and may not represent the actual circuitry. The duty cycle of CGMXCLK is unknown and may depend on the crystal and other external factors.
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Clock Generator Module (CGM) Addr. Register Name Bit 7 Read: $001C $001D $001E PLL Control Register Write: (PCTL) Reset: Read: PLL Bandwidth Control Register Write: (PBWC) Reset: Read: PLL Programming Register Write: (PPG) Reset: PLLIE 0 AUTO 6 PLLF 0 LOCK 5 4 PLLON BCS 1 0 ACQ XLD 3 2 1 Bit 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 MUL7 MUL6 MUL5 MUL4 VRS7 VRS6 VRS5 VRS4 0 1 1 0 0 1 1 0 = Unimplemented NOTES: 1.
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Clock Generator Module (CGM) PLLIE — PLL Interrupt Enable Bit This read/write bit enables the PLL to generate an interrupt request when the LOCK bit toggles, setting the PLL flag, PLLF. When the AUTO bit in the PLL bandwidth control register (PBWC) is clear, PLLIE cannot be written and reads as 0. Reset clears the PLLIE bit. 1 = PLL interrupts enabled 0 = PLL interrupts disabled PLLF — PLL Interrupt Flag Bit This read-only bit is set whenever the LOCK bit toggles.
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Clock Generator Module (CGM) the other. During the transition, CGMOUT is held in stasis. See 9.4.3 Base Clock Selector Circuit. Reset and the STOP instruction clear the BCS bit. 1 = CGMOUT driven by CGMVCLK/2 0 = CGMOUT driven by CGMXCLK/2 NOTE: PLLON and BCS have built-in protection that prevents the base clock selector circuit from selecting the VCO clock as the source of the base clock if the PLL is off. Therefore, PLLON cannot be cleared when BCS is set, and BCS cannot be set when PLLON is clear.
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Clock Generator Module (CGM) AUTO — Automatic Bandwidth Control Bit This read/write bit selects automatic or manual bandwidth control. When initializing the PLL for manual operation (AUTO = 0), the ACQ bit should be cleared before turning the PLL on. Reset clears the AUTO bit. 1 = Automatic bandwidth control 0 = Manual bandwidth control LOCK — Lock Indicator Bit When the AUTO bit is set, LOCK is a read-only bit that becomes set when the VCO clock CGMVCLK, is locked (running at the programmed frequency).
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Clock Generator Module (CGM) The crystal loss detect function works only when the BCS bit is set, selecting CGMVCLK to drive CGMOUT. When BCS is clear, XLD always reads as 0. Bits [3:0] — Reserved for test These bits enable test functions not available in user mode. To ensure software portability from development systems to user applications, software should write zeros to Bits [3:0] whenever writing to PBWC. 9.6.
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Clock Generator Module (CGM) Table 9-1. VCO Frequency Multiplier (N) Selection NOTE: MUL7:MUL6:MUL5:MUL4 VCO Frequency Multiplier (N) 0000 1 0001 1 0010 2 0011 3 1101 13 1110 14 1111 15 The multiplier select bits have built-in protection that prevents them from being written when the PLL is on (PLLON = 1). VRS[7:4] — VCO Range Select Bits These read/write bits control the hardware center-of-range linear multiplier L, which controls the hardware center-of-range frequency fVRS. (See 9.4.2.
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Clock Generator Module (CGM) 9.7 Interrupts When the AUTO bit is set in the PLL bandwidth control register (PBWC), the PLL can generate a CPU interrupt request every time the LOCK bit changes state. The PLLIE bit in the PLL control register (PCTL) enables CPU interrupts from the PLL. PLLF, the interrupt flag in the PCTL, becomes set whether interrupts are enabled or not. When the AUTO bit is clear, CPU interrupts from the PLL are disabled and PLLF reads as 0.
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Clock Generator Module (CGM) 9.8.2 Stop Mode When the STOP instruction executes, the SIM drives the SIMOSCEN signal low, disabling the CGM and holding low all CGM outputs (CGMXCLK, CGMOUT, and CGMINT). If the STOP instruction is executed with the VCO clock, CGMVCLK, divided by two driving CGMOUT, the PLL automatically clears the BCS bit in the PLL control register (PCTL), thereby selecting the crystal clock, CGMXCLK, divided by two as the source of CGMOUT.
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Clock Generator Module (CGM) 9.10.1 Acquisition/Lock Time Definitions Typical control systems refer to the acquisition time or lock time as the reaction time of the system, within specified tolerances, to a step input. In a PLL, the step input occurs when the PLL is turned on or when it suffers a noise hit. The tolerance is usually specified as a percentage of the step input or when the output settles to the desired value plus or minus a percentage of the frequency change.
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Clock Generator Module (CGM) • Lock time, tLOCK, is the time the PLL takes to reduce the error between the actual output frequency and the desired output frequency to less than the lock mode entry tolerance ∆LOCK. Lock time is based on an initial frequency error, (fDES – fORIG)/fDES, of not more than ±100%. In automatic bandwidth control mode, lock time expires when the LOCK bit becomes set in the PLL bandwidth control register (PBWC). See 9.4.2.3 Manual and Automatic PLL Bandwidth Modes.
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Clock Generator Module (CGM) Also important is the operating voltage potential applied to VDDA. The power supply potential alters the characteristics of the PLL. A fixed value is best. Variable supplies, such as batteries, are acceptable if they vary within a known range at very slow speeds. Noise on the power supply is not acceptable, because it causes small frequency errors which continually change the acquisition time of the PLL.
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Clock Generator Module (CGM) 9.10.4 Reaction Time Calculation The actual acquisition and lock times can be calculated using the equations below. These equations yield nominal values under the following conditions: • Correct selection of filter capacitor, CF, (see 9.10.3 Choosing a Filter Capacitor) • Room temperature operation • Negligible external leakage on CGMXFC • Negligible noise The K factor in the equations is derived from internal PLL parameters.
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Clock Generator Module (CGM) whether the PLL is within the lock mode entry tolerance ∆LOCK. Therefore, the acquisition time tACQ, is an integer multiple of nACQ/fRDV, and the acquisition to lock time tAL, is an integer multiple of nTRK/fRDV. Also, since the average frequency over the entire measurement period must be within the specified tolerance, the total time usually is longer than tLOCK as calculated above.
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Technical Data — MC68HC908AB32 Section 10. Monitor ROM (MON) 10.1 Contents 10.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 10.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 10.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .158 10.4.1 Entering Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 10.4.2 Data Format . . . . . . . . . . . . . . . .
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Monitor ROM (MON) 10.3 Features Features of the monitor ROM include the following: • Normal user-mode pin functionality • One pin dedicated to serial communication between monitor ROM and host computer • Standard mark/space non-return-to-zero (NRZ) communication with host computer • 4800 baud to 28.8 k-baud communication with host computer • FLASH memory security feature1 • Execution of code in RAM or FLASH 10.
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Monitor ROM (MON) VDD 10 kΩ MC68HC908AB32 RST 0.1 µF VTST 10 Ω IRQ VDDA VDDA VCGMXFC 1 10 µF 10 µF + + MC145407 + 3 18 4 17 2 0.1 µF 20 19 10 µF OSC1 + 10 µF VDD X1 4.9152 MHz 20 pF 10 MΩ OSC2 20 pF DB-25 2 5 16 3 6 15 VSS VDD VDD 7 0.1 µF VDD 1 MC74HC125 14 2 3 6 5 4 7 VDD 10 kΩ VDD VDD 10 kΩ 10 kΩ PTC0 PTC1 A NOTES: Position A — Bus clock = CGMXCLK ÷ 4 or CGMVCLK ÷ 4 Position B — Bus clock = CGMXCLK ÷ 2 (See NOTES) PTA0 PTC3 B Figure 10-1.
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Monitor ROM (MON) 10.4.1 Entering Monitor Mode Table 10-1 shows the pin conditions for entering monitor mode. 1 0 1 0 1 VTST PTC3 Pin PTC1 Pin (1) VTST PTA0 Pin IRQ Pin PTC0 Pin Table 10-1. Monitor Mode Entry Conditions CGMOUT Bus Frequency (CGMOUT ÷ 2) 1 1 CGMXCLK ÷ 2 or CGMVCLK ÷ 2 CGMXCLK ÷ 4 or CGMVCLK ÷ 4 0 CGMXCLK CGMXCLK ÷ 2 Notes: 1. For VTST, see Section 23. Electrical Specifications.
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Monitor ROM (MON) Table 10-2 is a summary of the differences between user mode and monitor mode. Table 10-2. Mode Differences Functions Modes COP Reset Vector High Reset Vector Low Break Vector High Break Vector Low SWI Vector High SWI Vector Low User Enabled $FFFE $FFFF $FFFC $FFFD $FFFC $FFFD Monitor Disabled(1) $FEFE $FEFF $FEFC $FEFD $FEFC $FEFD Notes: 1. If the high voltage (VTST) is removed from the IRQ pin while in monitor mode, the SIM asserts its COP enable output.
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Monitor ROM (MON) 10.4.3 Echoing As shown in Figure 10-4, the monitor ROM immediately echoes each received byte back to the PTA0 pin for error checking. Any result of a command appears after the echo of the last byte of the command. SENT TO MONITOR READ READ ADDR. HIGH ADDR. HIGH ADDR. LOW ADDR. LOW ECHO DATA RESULT Figure 10-4. Read Transaction 10.4.4 Break Signal A start bit followed by nine low bits is a break signal. (See Figure 10-5.
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Monitor ROM (MON) 10.4.5 Commands The monitor ROM uses these commands: • READ, read memory • WRITE, write memory • IREAD, indexed read • IWRITE, indexed write • READSP, read stack pointer • RUN, run user program A sequence of IREAD or IWRITE commands can access a block of memory sequentially over the full 64k-byte memory map. Table 10-3.
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Monitor ROM (MON) Table 10-4. WRITE (Write Memory) Command Description Write byte to memory Operand Specifics 2-byte address in high byte:low byte order; low byte followed by data byte Data Returned None Opcode $49 Command Sequence SENT TO MONITOR WRITE WRITE ADDRESS HIGH ADDRESS HIGH ADDRESS LOW ADDRESS LOW DATA DATA ECHO Table 10-5.
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Monitor ROM (MON) Table 10-6. IWRITE (Indexed Write) Command Description Write to last address accessed + 1 Operand Specifies single data byte Data Returned None Opcode $19 Command Sequence SENT TO MONITOR IWRITE IWRITE DATA DATA ECHO Table 10-7. READSP (Read Stack Pointer) Command Description Reads stack pointer Operand None Data Returned Returns stack pointer in high byte:low byte order Opcode $0C Command Sequence SENT TO MONITOR READSP READSP ECHO MC68HC908AB32 — Rev. 1.
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Monitor ROM (MON) Table 10-8. RUN (Run User Program) Command Description Executes RTI instruction Operand None Data Returned None Opcode $28 Command Sequence SENT TO MONITOR RUN RUN ECHO 10.4.6 Baud Rate With a 4.9152-MHz crystal and the PTC3 pin at logic 1 during reset, data is transferred between the monitor and host at 4800 baud. If the PTC3 pin is at logic 0 during reset, the monitor baud rate is 9600.
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Monitor ROM (MON) 10.5 Security A security feature discourages unauthorized reading of FLASH locations while in monitor mode. The host can bypass the security feature at monitor mode entry by sending eight security bytes that match the bytes at locations $FFF6–$FFFD. Locations $FFF6–$FFFD contain userdefined data. NOTE: Do not leave locations $FFF6–$FFFD blank. For security reasons, program locations $FFF6–$FFFD even if they are not used for vectors.
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Monitor ROM (MON) Upon power-on reset, if the received bytes of the security code do not match the data at locations $FFF6–$FFFD, the host fails to bypass the security feature. The MCU remains in monitor mode, but reading a FLASH location returns an invalid value and trying to execute code from FLASH causes an illegal address reset. After receiving the eight security bytes from the host, the MCU transmits a break character, signifying that it is ready to receive a command.
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Technical Data — MC68HC908AB32 Section 11. Timer Interface Module A (TIMA) 11.1 Contents 11.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 11.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 11.4 Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 11.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171 11.5.1 TIMA Counter Prescaler. . .
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Timer Interface Module A (TIMA) 11.2 Introduction This section describes the timer interface module A (TIMA). The TIMA is a four-channel timer that provides a timing reference with input capture, output compare, and pulse-width-modulation functions. Figure 11-1 is a block diagram of the TIMA. 11.
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Timer Interface Module A (TIMA) 11.4 Pin Name Conventions The TIMA share five I/O pins with port D, E, and F I/O pins. The full name of the TIMA I/O pin is listed in Table 11-1. The generic pin name appear in the text that follows. Table 11-1. Pin Name Conventions TIMA Generic Pin Names: Full TIMA Pin Names: TACLK PTD6/TACLK TACH0 PTE2/TACH0 TACH1 PTE3/TACH1 TACH2 PTF0/TACH2 TACH3 PTF1/TACH3 11.5 Functional Description Figure 11-1 shows the structure of the TIMA.
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Timer Interface Module A (TIMA) PTD6/TACLK PRESCALER SELECT INTERNAL BUS CLOCK PRESCALER TSTOP PS2 TRST PS1 PS0 16-BIT COUNTER TOF TOIE 16-BIT COMPARATOR INTERRUPT LOGIC TAMODH:TAMODL TOV0 CHANNEL 0 ELS0B ELS0A CH0MAX 16-BIT COMPARATOR TACH0H:TACH0L PTE2 LOGIC PTE2/TACH0 CH0F 16-BIT LATCH MS0A CH0IE INTERRUPT LOGIC MS0B INTERNAL BUS TOV1 CHANNEL 1 ELS1B ELS1A CH1MAX 16-BIT COMPARATOR TACH1H:TACH1L PTE3 LOGIC PTE3/TACH1 CH1F 16-BIT LATCH MS1A CH1IE INTERRUPT LOGIC TOV2 CH
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Timer Interface Module A (TIMA) Addr.
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Timer Interface Module A (TIMA) Addr.
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Timer Interface Module A (TIMA) 11.5.3 Output Compare With the output compare function, the TIMA can generate a periodic pulse with a programmable polarity, duration, and frequency. When the counter reaches the value in the registers of an output compare channel, the TIMA can set, clear, or toggle the channel pin. Output compares can generate TIMA CPU interrupt requests. 11.5.3.1 Unbuffered Output Compare Any output compare channel can generate unbuffered output compare pulses as described in 11.5.
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Timer Interface Module A (TIMA) 11.5.3.2 Buffered Output Compare Channels 0 and 1 can be linked to form a buffered output compare channel whose output appears on the PTE2/TACH0 pin. The TIMA channel registers of the linked pair alternately control the output. Setting the MS0B bit in TIMA channel 0 status and control register (TASC0) links channel 0 and channel 1. The output compare value in the TIMA channel 0 registers initially controls the output on the PTE2/TACH0 pin.
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Timer Interface Module A (TIMA) 11.5.4 Pulse Width Modulation (PWM) By using the toggle-on-overflow feature with an output compare channel, the TIMA can generate a PWM signal. The value in the TIMA counter modulo registers determines the period of the PWM signal. The channel pin toggles when the counter reaches the value in the TIMA counter modulo registers. The time between overflows is the period of the PWM signal.
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Timer Interface Module A (TIMA) 11.5.4.1 Unbuffered PWM Signal Generation Any output compare channel can generate unbuffered PWM pulses as described in 11.5.4 Pulse Width Modulation (PWM). The pulses are unbuffered because changing the pulse width requires writing the new pulse width value over the old value currently in the TIMA channel registers. An unsynchronized write to the TIMA channel registers to change a pulse width value could cause incorrect operation for up to two PWM periods.
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Timer Interface Module A (TIMA) 11.5.4.2 Buffered PWM Signal Generation Channels 0 and 1 can be linked to form a buffered PWM channel whose output appears on the PTE2/TACH0 pin. The TIMA channel registers of the linked pair alternately control the pulse width of the output. Setting the MS0B bit in TIMA channel 0 status and control register (TASC0) links channel 0 and channel 1. The TIMA channel 0 registers initially control the pulse width on the PTE2/TACH0 pin.
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Timer Interface Module A (TIMA) 11.5.4.3 PWM Initialization To ensure correct operation when generating unbuffered or buffered PWM signals, use the following initialization procedure: 1. In the TIMA status and control register (TASC): a. Stop the TIMA counter by setting the TIMA stop bit, TSTOP. b. Reset the TIMA counter by setting the TIMA reset bit, TRST. 2. In the TIMA counter modulo registers (TAMODH:TAMODL), write the value for the required PWM period. 3.
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Timer Interface Module A (TIMA) Setting MS2B links channels 2 and 3 and configures them for buffered PWM operation. The TIMA channel 2 registers (TACH2H:TACH2L) initially control the PWM output. TIMA channel 2 status and control register (TASC2) controls and monitors the PWM signal from the linked channels. MS2B takes priority over MS2A. Clearing the toggle-on-overflow bit, TOVx, inhibits output toggles on TIMA overflows.
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Timer Interface Module A (TIMA) 11.7.1 Wait Mode The TIMA remains active after the execution of a WAIT instruction. In wait mode the TIMA registers are not accessible by the CPU. Any enabled CPU interrupt request from the TIMA can bring the MCU out of wait mode. If TIMA functions are not required during wait mode, reduce power consumption by stopping the TIMA before executing the WAIT instruction. 11.7.2 Stop Mode The TIMA is inactive after the execution of a STOP instruction.
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Timer Interface Module A (TIMA) 11.9 I/O Signals Ports E and F each share two pins with the TIMA and port D shares one. PTD6/TACLK is an external clock input to the TIMA prescaler. The four TIMA channel I/O pins are PTE2/TACH0, PTE3/TACH1, PTF0/TACH2, and PTF1/TACH3. 11.9.1 TIMA Clock Pin PTD6/TACLK is an external clock input that can be the clock source for the TIMA counter instead of the prescaled internal bus clock.
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Timer Interface Module A (TIMA) 11.10 I/O Registers The following I/O registers control and monitor operation of the TIMA: • TIMA status and control register (TASC) • TIMA counter registers (TACNTH:TACNTL) • TIMA counter modulo registers (TAMODH:TAMODL) • TIMA channel status and control registers (TASC0, TASC1, TASC2, and TASC3) • TIMA channel registers (TACH0H:TACH0L, TACH1H:TACH1L, TACH2H:TACH2L, and TACH3H:TACH3L) 11.10.
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Timer Interface Module A (TIMA) TOF — TIMA Overflow Flag Bit This read/write flag is set when the TIMA counter resets to $0000 after reaching the modulo value programmed in the TIMA counter modulo registers. Clear TOF by reading the TIMA status and control register when TOF is set and then writing a logic zero to TOF. If another TIMA overflow occurs before the clearing sequence is complete, then writing logic zero to TOF has no effect.
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Timer Interface Module A (TIMA) PS[2:0] — Prescaler Select Bits These read/write bits select either the PTD6/TACLK pin or one of the seven prescaler outputs as the input to the TIMA counter as Table 11-2 shows. Reset clears the PS[2:0] bits. Table 11-2.
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Timer Interface Module A (TIMA) Address: Read: $0023 Bit 7 6 5 4 3 2 1 Bit 0 Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 Write: Reset: = Unimplemented Figure 11-6. TIMA Counter Register Low (TACNTL) 11.10.3 TIMA Counter Modulo Registers The read/write TIMA modulo registers contain the modulo value for the TIMA counter. When the TIMA counter reaches the modulo value, the overflow flag (TOF) becomes set, and the TIMA counter resumes counting from $0000 at the next clock.
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Timer Interface Module A (TIMA) 11.10.
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Timer Interface Module A (TIMA) Address: $002C Bit 7 Read: CH2F Write: 0 Reset: 0 6 5 4 3 2 1 Bit 0 CH2IE MS2B MS2A ELS2B ELS2A TOV2 CH2MAX 0 0 0 0 0 0 0 Figure 11-11. TIMA Channel 2 Status and Control Register (TASC2) Address: $002F Bit 7 Read: CH3F Write: 0 Reset: 0 6 CH3IE 0 5 0 0 4 3 2 1 Bit 0 MS3A ELS3B ELS3A TOV3 CH3MAX 0 0 0 0 0 Figure 11-12.
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Timer Interface Module A (TIMA) MSxB — Mode Select Bit B This read/write bit selects buffered output compare/PWM operation. MSxB exists only in the TIMA channel 0 and TIMA channel 2 status and control registers. Setting MS0B disables the channel 1 status and control register and reverts TCH1B to general-purpose I/O. Setting MS2B disables the channel 3 status and control register and reverts TCH3B to general-purpose I/O. Reset clears the MSxB bit.
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Timer Interface Module A (TIMA) Table 11-3.
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Timer Interface Module A (TIMA) OVERFLOW OVERFLOW OVERFLOW OVERFLOW OVERFLOW PERIOD TACHx OUTPUT COMPARE OUTPUT COMPARE OUTPUT COMPARE OUTPUT COMPARE CHxMAX Figure 11-13. CHxMAX Latency 11.10.5 TIMA Channel Registers These read/write registers contain the captured TIMA counter value of the input capture function or the output compare value of the output compare function. The state of the TIMA channel registers after reset is unknown.
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Timer Interface Module A (TIMA) Address: Read: Write: $002A Bit 7 6 5 4 3 2 1 Bit 0 Bit 15 14 13 12 11 10 9 Bit 8 Reset: Indeterminate after reset Figure 11-16. TIMA Channel 1 Register High (TACH1H) Address: Read: Write: $002B Bit 7 6 5 4 3 2 1 Bit 0 Bit 7 6 5 4 3 2 1 Bit 0 Reset: Indeterminate after reset Figure 11-17.
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Timer Interface Module A (TIMA) Address: Read: Write: $0030 Bit 7 6 5 4 3 2 1 Bit 0 Bit 15 14 13 12 11 10 9 Bit 8 Reset: Indeterminate after reset Figure 11-20. TIMA Channel 3 Register High (TACH3H) Address: Read: Write: Reset: $0031 Bit 7 6 5 4 3 2 1 Bit 0 Bit 7 6 5 4 3 2 1 Bit 0 Indeterminate after reset Figure 11-21. TIMA Channel 3 Register Low (TACH3L) Technical Data 194 MC68HC908AB32 — Rev. 1.
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Technical Data — MC68HC908AB32 Section 12. Timer Interface Module B (TIMB) 12.1 Contents 12.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 12.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 12.4 Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 12.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .197 12.5.1 TIMB Counter Prescaler. . .
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Timer Interface Module B (TIMB) 12.2 Introduction This section describes the timer interface module A (TIMB). The TIMB is a four-channel timer that provides a timing reference with input capture, output compare, and pulse-width-modulation functions. Figure 12-1 is a block diagram of the TIMB. 12.
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Timer Interface Module B (TIMB) 12.4 Pin Name Conventions The TIMB share five I/O pins with port D and F I/O pins. The full name of the TIMB I/O pin is listed in Table 12-1. The generic pin name appear in the text that follows. Table 12-1. Pin Name Conventions TIMB Generic Pin Names: Full TIMB Pin Names: TBCLK PTD4/TBCLK TBCH0 PTF4/TBCH0 TBCH1 PTF5/TBCH1 TBCH2 PTF2/TBCH2 TBCH3 PTF3/TBCH3 12.5 Functional Description Figure 12-1 shows the structure of the TIMB.
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Timer Interface Module B (TIMB) PTD4/TBCLK PRESCALER SELECT INTERNAL BUS CLOCK PRESCALER TSTOP PS2 TRST PS1 PS0 16-BIT COUNTER TOF TOIE 16-BIT COMPARATOR INTERRUPT LOGIC TBMODH:TBMODL TOV0 CHANNEL 0 ELS0B ELS0A CH0MAX 16-BIT COMPARATOR TBCH0H:TBCH0L PTF4 LOGIC PTF4/TBCH0 CH0F 16-BIT LATCH MS0A CH0IE INTERRUPT LOGIC MS0B INTERNAL BUS TOV1 CHANNEL 1 ELS1B ELS1A CH1MAX 16-BIT COMPARATOR TBCH1H:TBCH1L PTF5 LOGIC PTF5/TBCH1 CH1F 16-BIT LATCH MS1A CH1IE INTERRUPT LOGIC TOV2 CH
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Timer Interface Module B (TIMB) Addr.
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Timer Interface Module B (TIMB) Addr.
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Timer Interface Module B (TIMB) 12.5.3 Output Compare With the output compare function, the TIMB can generate a periodic pulse with a programmable polarity, duration, and frequency. When the counter reaches the value in the registers of an output compare channel, the TIMB can set, clear, or toggle the channel pin. Output compares can generate TIMB CPU interrupt requests. 12.5.3.1 Unbuffered Output Compare Any output compare channel can generate unbuffered output compare pulses as described in 12.5.
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Timer Interface Module B (TIMB) 12.5.3.2 Buffered Output Compare Channels 0 and 1 can be linked to form a buffered output compare channel whose output appears on the PTF4/TBCH0 pin. The TIMB channel registers of the linked pair alternately control the output. Setting the MS0B bit in TIMB channel 0 status and control register (TBSC0) links channel 0 and channel 1. The output compare value in the TIMB channel 0 registers initially controls the output on the PTF4/TBCH0 pin.
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Timer Interface Module B (TIMB) 12.5.4 Pulse Width Modulation (PWM) By using the toggle-on-overflow feature with an output compare channel, the TIMB can generate a PWM signal. The value in the TIMB counter modulo registers determines the period of the PWM signal. The channel pin toggles when the counter reaches the value in the TIMB counter modulo registers. The time between overflows is the period of the PWM signal.
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Timer Interface Module B (TIMB) 12.5.4.1 Unbuffered PWM Signal Generation Any output compare channel can generate unbuffered PWM pulses as described in 12.5.4 Pulse Width Modulation (PWM). The pulses are unbuffered because changing the pulse width requires writing the new pulse width value over the old value currently in the TIMB channel registers. An unsynchronized write to the TIMB channel registers to change a pulse width value could cause incorrect operation for up to two PWM periods.
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Timer Interface Module B (TIMB) 12.5.4.2 Buffered PWM Signal Generation Channels 0 and 1 can be linked to form a buffered PWM channel whose output appears on the PTF4/TBCH0 pin. The TIMB channel registers of the linked pair alternately control the pulse width of the output. Setting the MS0B bit in TIMB channel 0 status and control register (TBSC0) links channel 0 and channel 1. The TIMB channel 0 registers initially control the pulse width on the PTF4/TBCH0 pin.
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Timer Interface Module B (TIMB) 12.5.4.3 PWM Initialization To ensure correct operation when generating unbuffered or buffered PWM signals, use the following initialization procedure: 1. In the TIMB status and control register (TBSC): a. Stop the TIMB counter by setting the TIMB stop bit, TSTOP. b. Reset the TIMB counter by setting the TIMB reset bit, TRST. 2. In the TIMB counter modulo registers (TBMODH:TBMODL), write the value for the required PWM period. 3.
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Timer Interface Module B (TIMB) Setting MS2B links channels 2 and 3 and configures them for buffered PWM operation. The TIMB channel 2 registers (TBCH2H:TBCH2L) initially control the PWM output. TIMB channel 2 status and control register (TBSC2) controls and monitors the PWM signal from the linked channels. MS2B takes priority over MS2A. Clearing the toggle-on-overflow bit, TOVx, inhibits output toggles on TIMB overflows.
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Timer Interface Module B (TIMB) 12.7.1 Wait Mode The TIMB remains active after the execution of a WAIT instruction. In wait mode the TIMB registers are not accessible by the CPU. Any enabled CPU interrupt request from the TIMB can bring the MCU out of wait mode. If TIMB functions are not required during wait mode, reduce power consumption by stopping the TIMB before executing the WAIT instruction. 12.7.2 Stop Mode The TIMB is inactive after the execution of a STOP instruction.
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Timer Interface Module B (TIMB) 12.9 I/O Signals Port F shares four pins with the TIMB and port D shares one. PTD4/TBCLK is an external clock input to the TIMB prescaler. The four TIMB channel I/O pins are PTF4/TBCH0, PTF5/TBCH1, PTF2/TBCH2, and PTF3/TBCH3. 12.9.1 TIMB Clock Pin PTD4/TBCLK is an external clock input that can be the clock source for the TIMB counter instead of the prescaled internal bus clock. Select the PTD4/TBCLK input by writing logic 1s to the three prescaler select bits, PS[2:0].
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Timer Interface Module B (TIMB) 12.10 I/O Registers The following I/O registers control and monitor operation of the TIMB: • TIMB status and control register (TBSC) • TIMB counter registers (TBCNTH:TBCNTL) • TIMB counter modulo registers (TBMODH:TBMODL) • TIMB channel status and control registers (TBSC0, TBSC1, TBSC2, and TBSC3) • TIMB channel registers (TBCH0H:TBCH0L, TBCH1H:TBCH1L, TBCH2H:TBCH2L, and TBCH3H:TBCH3L) 12.10.
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Timer Interface Module B (TIMB) TOF — TIMB Overflow Flag Bit This read/write flag is set when the TIMB counter resets to $0000 after reaching the modulo value programmed in the TIMB counter modulo registers. Clear TOF by reading the TIMB status and control register when TOF is set and then writing a logic zero to TOF. If another TIMB overflow occurs before the clearing sequence is complete, then writing logic zero to TOF has no effect.
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Timer Interface Module B (TIMB) PS[2:0] — Prescaler Select Bits These read/write bits select either the PTD4/TBCLK pin or one of the seven prescaler outputs as the input to the TIMB counter as Table 12-2 shows. Reset clears the PS[2:0] bits. Table 12-2.
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Timer Interface Module B (TIMB) Address: Read: $0042 Bit 7 6 5 4 3 2 1 Bit 0 Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 Write: Reset: = Unimplemented Figure 12-6. TIMB Counter Register Low (TBCNTL) 12.10.3 TIMB Counter Modulo Registers The read/write TIMB modulo registers contain the modulo value for the TIMB counter. When the TIMB counter reaches the modulo value, the overflow flag (TOF) becomes set, and the TIMB counter resumes counting from $0000 at the next clock.
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Timer Interface Module B (TIMB) 12.10.
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Timer Interface Module B (TIMB) Address: $0032 Bit 7 Read: CH2F Write: 0 Reset: 0 6 5 4 3 2 1 Bit 0 CH2IE MS2B MS2A ELS2B ELS2A TOV2 CH2MAX 0 0 0 0 0 0 0 Figure 12-11. TIMB Channel 2 Status and Control Register (TBSC2) Address: $0035 Bit 7 Read: CH3F Write: 0 Reset: 0 6 CH3IE 0 5 0 0 4 3 2 1 Bit 0 MS3A ELS3B ELS3A TOV3 CH3MAX 0 0 0 0 0 Figure 12-12.
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Timer Interface Module B (TIMB) MSxB — Mode Select Bit B This read/write bit selects buffered output compare/PWM operation. MSxB exists only in the TIMB channel 0 and TIMB channel 2 status and control registers. Setting MS0B disables the channel 1 status and control register and reverts TCH1B to general-purpose I/O. Setting MS2B disables the channel 3 status and control register and reverts TCH3B to general-purpose I/O. Reset clears the MSxB bit.
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Timer Interface Module B (TIMB) Table 12-3.
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Timer Interface Module B (TIMB) OVERFLOW OVERFLOW OVERFLOW OVERFLOW OVERFLOW PERIOD TBCHx OUTPUT COMPARE OUTPUT COMPARE OUTPUT COMPARE OUTPUT COMPARE CHxMAX Figure 12-13. CHxMAX Latency 12.10.5 TIMB Channel Registers These read/write registers contain the captured TIMB counter value of the input capture function or the output compare value of the output compare function. The state of the TIMB channel registers after reset is unknown.
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Timer Interface Module B (TIMB) Address: Read: Write: $0049 Bit 7 6 5 4 3 2 1 Bit 0 Bit 15 14 13 12 11 10 9 Bit 8 Reset: Indeterminate after reset Figure 12-16. TIMB Channel 1 Register High (TBCH1H) Address: Read: Write: $004A Bit 7 6 5 4 3 2 1 Bit 0 Bit 7 6 5 4 3 2 1 Bit 0 Reset: Indeterminate after reset Figure 12-17.
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Timer Interface Module B (TIMB) Address: Read: Write: $0036 Bit 7 6 5 4 3 2 1 Bit 0 Bit 15 14 13 12 11 10 9 Bit 8 Reset: Indeterminate after reset Figure 12-20. TIMB Channel 3 Register High (TBCH3H) Address: Read: Write: Reset: $0037 Bit 7 6 5 4 3 2 1 Bit 0 Bit 7 6 5 4 3 2 1 Bit 0 Indeterminate after reset Figure 12-21. TIMB Channel 3 Register Low (TBCH3L) Technical Data 220 MC68HC908AB32 — Rev. 1.
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Technical Data — MC68HC908AB32 Section 13. Programmable Interrupt Timer (PIT) 13.1 Contents 13.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 13.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 13.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .222 13.4.1 PIT Counter Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 13.5 Low-Power Modes . . . . . . .
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Programmable Interrupt Timer (PIT) 13.3 Features Features of the PIT include the following: • Programmable PIT clock input • Free-running or modulo up-count operation • PIT counter stop and reset bits 13.4 Functional Description Figure 13-1 shows the structure of the PIT. The central component of the PIT is the 16-bit PIT counter that can operate as a free-running counter or a modulo up-counter. The counter provides the timing reference for the interrupt.
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Programmable Interrupt Timer (PIT) Addr.
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Programmable Interrupt Timer (PIT) 13.5 Low-Power Modes The WAIT and STOP instructions put the MCU in low-powerconsumption standby modes. 13.5.1 Wait Mode The PIT remains active after the execution of a WAIT instruction. In wait mode the PIT registers are not accessible by the CPU. Any enabled CPU interrupt request from the PIT can bring the MCU out of wait mode. If PIT functions are not required during wait mode, reduce power consumption by stopping the PIT before executing the WAIT instruction. 13.5.
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Programmable Interrupt Timer (PIT) bits. Some status bits have a two-step read/write clearing procedure. If software does the first step on such a bit before the break, the bit cannot change during the break state as long as BCFE is at logic zero. After the break, doing the second step clears the status bit. 13.
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Programmable Interrupt Timer (PIT) POF — PIT Overflow Flag Bit This read/write flag is set when the PIT counter resets to $0000 after reaching the modulo value programmed in the PIT counter modulo registers. Clear POF by reading the PIT status and control register when POF is set and then writing a logic zero to POF. If another PIT overflow occurs before the clearing sequence is complete, then writing logic zero to POF has no effect.
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Programmable Interrupt Timer (PIT) PPS[2:0] — PIT Prescaler Select Bits These read/write bits select one of the seven prescaler outputs as the input to the PIT counter as Table 13-1 shows. Reset clears the PPS[2:0] bits. Table 13-1.
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Programmable Interrupt Timer (PIT) Address: Read: $004D Bit 7 6 5 4 3 2 1 Bit 0 Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 Write: Reset: = Unimplemented Figure 13-5. PIT Counter Register Low (PCNTL) 13.7.3 PIT Counter Modulo Registers The read/write PIT modulo registers contain the modulo value for the PIT counter. When the PIT counter reaches the modulo value, the overflow flag (POF) becomes set, and the PIT counter resumes counting from $0000 at the next clock.
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Technical Data — MC68HC908AB32 Section 14. Analog-to-Digital Converter (ADC) 14.1 Contents 14.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 14.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 14.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .231 14.4.1 ADC Port I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 14.4.2 Voltage Conversion . . . .
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Analog-to-Digital Converter (ADC) 14.2 Introduction This section describes the 8-bit analog-to-digital converter (ADC). 14.3 Features Features of the ADC module include: Addr.
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Analog-to-Digital Converter (ADC) 14.4 Functional Description The ADC provides eight pins for sampling external sources at pins PTB7/ATD7–PTB0/ATD0. An analog multiplexer allows the single ADC converter to select one of eight ADC channels as ADC voltage in (VADIN). VADIN is converted by the successive approximation register-based analog-to-digital converter. When the conversion is completed, ADC places the result in the ADC data register and sets a flag or generates an interrupt. (See Figure 14-2.
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Analog-to-Digital Converter (ADC) 14.4.1 ADC Port I/O Pins PTB7/ATD7–PTB0/ATD0 are general-purpose I/O (input/output) pins that share with the ADC channels. The channel select bits define which ADC channel/port pin will be used as the input signal. The ADC overrides the port I/O logic by forcing that pin as input to the ADC. The remaining ADC channels/port pins are controlled by the port I/O logic and can be used as general-purpose I/O.
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Analog-to-Digital Converter (ADC) 14.4.5 Accuracy and Precision The conversion process is monotonic and has no missing codes. 14.5 Interrupts When the AIEN bit is set, the ADC module is capable of generating CPU interrupts after each ADC conversion. A CPU interrupt is generated if the COCO bit is at logic 0. The COCO bit is not used as a conversion complete flag when interrupts are enabled. 14.6 Low-Power Modes The WAIT and STOP instruction can put the MCU in low powerconsumption standby modes. 14.6.
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Analog-to-Digital Converter (ADC) 14.7.1 ADC Analog Power Pin (VDDAREF) The ADC analog portion uses VDDAREF as its power pin. Connect the VDDAREF pin to the same voltage potential as VDD. External filtering may be necessary to ensure clean VDDAREF for good results. NOTE: For maximum noise immunity, route VDDAREF carefully and place bypass capacitors as close as possible to the package. 14.7.2 ADC Analog Ground Pin (AVSS/VREFL) The ADC analog portion uses AVSS/VREFL as its ground pin.
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Analog-to-Digital Converter (ADC) 14.8.1 ADC Status and Control Register (ADSCR) Function of the ADC status and control register is described here. Address: Read: Write: Reset: $0038 Bit 7 6 5 4 3 2 1 Bit 0 COCO AIEN ADCO ADCH4 ADCH3 ADCH2 ADCH1 ADCH0 0 0 0 1 1 1 1 1 Figure 14-3.
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Analog-to-Digital Converter (ADC) ADCH[4:0] — ADC Channel Select Bits ADCH[4:0] form a 5-bit field which is used to select one of the eight ADC channels, ATD7–ATD0. The channels are detailed in Table 14-1. Care should be taken when using a port pin as both an analog and digital input simultaneously to prevent switching noise from corrupting the analog signal. The ADC subsystem is turned off when the channel select bits are all set to 1.
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Analog-to-Digital Converter (ADC) 14.8.2 ADC Data Register (ADR) One 8-bit result register, ADC data register (ADR), is provided. This register is updated each time an ADC conversion completes. Address: Read: $0039 Bit 7 6 5 4 3 2 1 Bit 0 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 0 0 0 0 0 0 0 0 Write: Reset: = Unimplemented Figure 14-4. ADC Data Register (ADR) 14.8.3 ADC Clock Register (ADCLK) The ADC clock register (ADCLK) selects the clock frequency for the ADC.
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Analog-to-Digital Converter (ADC) Table 14-2. ADC Clock Divide Ratio ADIV2 ADIV1 ADIV0 ADC Clock Rate 0 0 0 ADC input clock ÷ 1 0 0 1 ADC input clock ÷ 2 0 1 0 ADC input clock ÷ 4 0 1 1 ADC input clock ÷ 8 1 X X ADC input clock ÷ 16 X = don’t care ADICLK — ADC Input Clock Select Bit ADICLK selects either the bus clock or CGMXCLK as the input clock source to generate the internal ADC clock. Reset selects CGMXCLK as the ADC clock source.
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Technical Data — MC68HC908AB32 Section 15. Serial Communications Interface Module (SCI) 15.1 Contents 15.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 15.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 15.4 Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 15.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .242 15.5.1 Data Format . .
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Serial Communications Interface 15.8.2 PTE1/RxD (Receive Data) . . . . . . . . . . . . . . . . . . . . . . . . . 260 15.9 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 15.9.1 SCI Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 15.9.2 SCI Control Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264 15.9.3 SCI Control Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 15.9.
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Serial Communications Interface Module (SCI) • Two receiver wakeup methods: – Idle line wakeup – Address mark wakeup • Interrupt-driven operation with eight interrupt flags: – Transmitter empty – Transmission complete – Receiver full – Idle receiver input – Receiver overrun – Noise error – Framing error – Parity error • Receiver framing error detection • Hardware parity checking • 1/16 bit-time noise detection MC68HC908AB32 — Rev. 1.
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Serial Communications Interface 15.4 Pin Name Conventions The generic names of the SCI I/O pins are: • RxD (receive data) • TxD (transmit data) SCI I/O (input/output) lines are implemented by sharing parallel I/O port pins. The full name of an SCI input or output reflects the name of the shared port pin. Table 15-1 shows the full names and the generic names of the SCI I/O pins. The generic pin names appear in the text of this section. Table 15-1.
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Serial Communications Interface Module (SCI) INTERNAL BUS SCI DATA REGISTER ERROR INTERRUPT CONTROL RECEIVER INTERRUPT CONTROL DMA INTERRUPT CONTROL RECEIVE SHIFT REGISTER PTE1/RxD TRANSMITTER INTERRUPT CONTROL SCI DATA REGISTER TRANSMIT SHIFT REGISTER PTE0/TxD TXINV SCTIE R8 TCIE T8 SCRIE ILIE R TE SCTE RE R TC RWU SBK SCRF OR ORIE IDLE NF NEIE FE FEIE PE PEIE LOOPS LOOPS FLAG CONTROL RECEIVE CONTROL WAKEUP CONTROL ENSCI ENSCI TRANSMIT CONTROL BKF M RPF WAKE ILTY C
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Serial Communications Interface Addr.
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Serial Communications Interface Module (SCI) 15.5.1 Data Format The SCI uses the standard non-return-to-zero mark/space data format illustrated in Figure 15-3. 8-BIT DATA FORMAT BIT M IN SCC1 CLEAR START BIT START BIT BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 PARITY BIT BIT 6 BIT 7 9-BIT DATA FORMAT BIT M IN SCC1 SET BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 STOP BIT NEXT START BIT PARITY BIT BIT 6 BIT 7 BIT 8 STOP BIT NEXT START BIT Figure 15-3. SCI Data Formats 15.5.
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Serial Communications Interface INTERNAL BUS ÷ 16 SCI DATA REGISTER SCP1 11-BIT TRANSMIT SHIFT REGISTER STOP SCP0 SCR1 H SCR2 7 6 5 4 3 2 1 0 L PTE0/TxD MSB TXINV PEN PTY PARITY GENERATION T8 R R SCTIE SCTE R SCTE SCTIE TC TCIE BREAK ALL 0s M LOAD FROM SCDR TRANSMITTER DMA SERVICE REQUEST TRANSMITTER CPU INTERRUPT REQUEST SCR0 8 START BAUD DIVIDER PREAMBLE ALL 1s PRESCALER ÷4 SHIFT ENABLE CGMXCLK TRANSMITTER CONTROL LOGIC SCTE SBK LOOPS SCTIE ENSCI TC TE TCIE Fig
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Serial Communications Interface Module (SCI) 15.5.2.1 Character Length The transmitter can accommodate either 8-bit or 9-bit data. The state of the M bit in SCI control register 1 (SCC1) determines character length. When transmitting 9-bit data, bit T8 in SCI control register 3 (SCC3) is the ninth bit (bit 8). 15.5.2.2 Character Transmission During an SCI transmission, the transmit shift register shifts a character out to the PTE0/TxD pin.
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Serial Communications Interface 15.5.2.3 Break Characters Writing a logic 1 to the send break bit, SBK, in SCC2 loads the transmit shift register with a break character. A break character contains all logic 0s and has no start, stop, or parity bit. Break character length depends on the M bit in SCC1. As long as SBK is at logic 1, transmitter logic continuously loads break characters into the transmit shift register.
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Serial Communications Interface Module (SCI) NOTE: When queueing an idle character, return the TE bit to logic 1 before the stop bit of the current character shifts out to the TxD pin. Setting TE after the stop bit appears on TxD causes data previously written to the SCDR to be lost. Toggle the TE bit for a queued idle character when the SCTE bit becomes set and just before writing the next byte to the SCDR. 15.5.2.
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Serial Communications Interface 15.5.3 Receiver Figure 15-5 shows the structure of the SCI receiver. 15.5.3.1 Character Length The receiver can accommodate either 8-bit or 9-bit data. The state of the M bit in SCI control register 1 (SCC1) determines character length. When receiving 9-bit data, bit R8 in SCI control register 2 (SCC2) is the ninth bit (bit 8). When receiving 8-bit data, bit R8 is a copy of the eighth bit (bit 7). 15.5.3.
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Serial Communications Interface Module (SCI) INTERNAL BUS SCR1 SCR2 SCP0 SCR0 BAUD DIVIDER ÷ 16 DATA RECOVERY PTE1/RxD CPU INTERRUPT REQUEST 8 7 6 5 M WAKE ILTY PEN PTY 4 3 2 1 0 L ALL 0s RPF ERROR CPU INTERRUPT REQUEST DMA SERVICE REQUEST H ALL 1s BKF 11-BIT RECEIVE SHIFT REGISTER STOP PRESCALER MSB ÷4 CGMXCLK SCI DATA REGISTER START SCP1 SCRF WAKEUP LOGIC PARITY CHECKING IDLE ILIE R SCRF SCRIE R SCRF SCRIE R OR ORIE NF NEIE FE FEIE PE PEIE RWU IDLE R8 ILIE SCRIE R OR O
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Serial Communications Interface 15.5.3.3 Data Sampling The receiver samples the PTE1/RxD pin at the RT clock rate. The RT clock is an internal signal with a frequency 16 times the baud rate.
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Serial Communications Interface Module (SCI) To verify the start bit and to detect noise, data recovery logic takes samples at RT3, RT5, and RT7. Table 15-2 summarizes the results of the start bit verification samples. Table 15-2.
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Serial Communications Interface NOTE: The RT8, RT9, and RT10 samples do not affect start bit verification. If any or all of the RT8, RT9, and RT10 start bit samples are logic 1s following a successful start bit verification, the noise flag (NF) is set and the receiver assumes that the bit is a start bit. To verify a stop bit and to detect noise, recovery logic takes samples at RT8, RT9, and RT10. Table 15-4 summarizes the results of the stop bit samples. Table 15-4.
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Serial Communications Interface Module (SCI) tolerance is much more than the degree of misalignment that is likely to occur. As the receiver samples an incoming character, it resynchronizes the RT clock on any valid falling edge within the character. Resynchronization within characters corrects misalignments between transmitter bit times and receiver bit times. Slow Data Tolerance Figure 15-7 shows how much a slow received character can be misaligned without causing a noise error or a framing error.
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Serial Communications Interface With the misaligned character shown in Figure 15-7, the receiver counts 170 RT cycles at the point when the count of the transmitting device is 10 bit times × 16 RT cycles + 3 RT cycles = 163 RT cycles. The maximum percent difference between the receiver count and the transmitter count of a slow 9-bit character with no errors is 170 – 163 × 100 = 4.
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Serial Communications Interface Module (SCI) For a 9-bit character, data sampling of the stop bit takes the receiver 10 bit times × 16 RT cycles + 10 RT cycles = 170 RT cycles. With the misaligned character shown in Figure 15-8, the receiver counts 170 RT cycles at the point when the count of the transmitting device is 11 bit times × 16 RT cycles = 176 RT cycles.
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Serial Communications Interface SCI receiver full bit, SCRF. The idle line type bit, ILTY, determines whether the receiver begins counting logic 1s as idle character bits after the start bit or after the stop bit. NOTE: With the WAKE bit clear, setting the RWU bit after the RxD pin has been idle may cause the receiver to wake up immediately. 15.5.3.
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Serial Communications Interface Module (SCI) • Framing error (FE) — The FE bit in SCS1 is set when a logic 0 occurs where the receiver expects a stop bit. The framing error interrupt enable bit, FEIE, in SCC3 enables FE to generate SCI error CPU interrupt requests. • Parity error (PE) — The PE bit in SCS1 is set when the SCI detects a parity error in incoming data. The parity error interrupt enable bit, PEIE, in SCC3 enables PE to generate SCI error CPU interrupt requests. 15.
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Serial Communications Interface 15.7 SCI During Break Module Interrupts The system integration module (SIM) controls whether status bits in other modules can be cleared during the break state. The BCFE bit in the SIM break flag control register (SBFCR) enables software to clear status bits during the break state. To allow software to clear status bits during a break interrupt, write a logic 1 to the BCFE bit.
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Serial Communications Interface Module (SCI) 15.9 I/O Registers These I/O registers control and monitor SCI operation: • SCI control register 1 (SCC1) • SCI control register 2 (SCC2) • SCI control register 3 (SCC3) • SCI status register 1 (SCS1) • SCI status register 2 (SCS2) • SCI data register (SCDR) • SCI baud rate register (SCBR) 15.9.
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Serial Communications Interface Address: Read: Write: Reset: $0013 Bit 7 6 5 4 3 2 1 Bit 0 LOOPS ENSCI TXINV M WAKE ILTY PEN PTY 0 0 0 0 0 0 0 0 Figure 15-9. SCI Control Register 1 (SCC1) LOOPS — Loop Mode Select Bit This read/write bit enables loop mode operation. In loop mode the PTE1/RxD pin is disconnected from the SCI, and the transmitter output goes into the receiver input. Both the transmitter and the receiver must be enabled to use loop mode. Reset clears the LOOPS bit.
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Serial Communications Interface Module (SCI) M — Mode (Character Length) Bit This read/write bit determines whether SCI characters are eight or nine bits long. (See Table 15-5.) The ninth bit can serve as an extra stop bit, as a receiver wakeup signal, or as a parity bit. Reset clears the M bit.
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Serial Communications Interface PTY — Parity Bit This read/write bit determines whether the SCI generates and checks for odd parity or even parity. (See Table 15-5.) Reset clears the PTY bit. 1 = Odd parity 0 = Even parity NOTE: Changing the PTY bit in the middle of a transmission or reception can generate a parity error. Table 15-5.
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Serial Communications Interface Module (SCI) • Enables the transmitter • Enables the receiver • Enables SCI wakeup • Transmits SCI break characters Address: Read: Write: Reset: $0014 Bit 7 6 5 4 3 2 1 Bit 0 SCTIE TCIE SCRIE ILIE TE RE RWU SBK 0 0 0 0 0 0 0 0 Figure 15-10. SCI Control Register 2 (SCC2) SCTIE — SCI Transmit Interrupt Enable Bit This read/write bit enables the SCTE bit to generate SCI transmitter CPU interrupt requests. Reset clears the SCTIE bit.
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Serial Communications Interface TE — Transmitter Enable Bit Setting this read/write bit begins the transmission by sending a preamble of 10 or 11 logic 1s from the transmit shift register to the PTE0/TxD pin. If software clears the TE bit, the transmitter completes any transmission in progress before the PTE0/TxD returns to the idle condition (logic 1). Clearing and then setting TE during a transmission queues an idle character to be sent after the character currently being transmitted.
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Serial Communications Interface Module (SCI) SBK — Send Break Bit Setting and then clearing this read/write bit transmits a break character followed by a logic 1. The logic 1 after the break character guarantees recognition of a valid start bit. If SBK remains set, the transmitter continuously transmits break characters with no logic 1s between them. Reset clears the SBK bit.
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Serial Communications Interface R8 — Received Bit 8 When the SCI is receiving 9-bit characters, R8 is the read-only ninth bit (bit 8) of the received character. R8 is received at the same time that the SCDR receives the other 8 bits. When the SCI is receiving 8-bit characters, R8 is a copy of the eighth bit (bit 7). Reset has no effect on the R8 bit. T8 — Transmitted Bit 8 When the SCI is transmitting 9-bit characters, T8 is the read/write ninth bit (bit 8) of the transmitted character.
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Serial Communications Interface Module (SCI) 15.9.
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Serial Communications Interface TC — Transmission Complete Bit This read-only bit is set when the SCTE bit is set, and no data, preamble, or break character is being transmitted. TC generates an SCI transmitter CPU interrupt request if the TCIE bit in SCC2 is also set. TC is automatically cleared when data, preamble or break is queued and ready to be sent. There may be up to 1.5 transmitter clocks of latency between queueing data, preamble, and break and the transmission actually starting.
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Serial Communications Interface Module (SCI) bit in SCC3 is also set. The data in the shift register is lost, but the data already in the SCDR is not affected. Clear the OR bit by reading SCS1 with OR set and then reading the SCDR. Reset clears the OR bit. 1 = Receive shift register full and SCRF = 1 0 = No receiver overrun Software latency may allow an overrun to occur between reads of SCS1 and SCDR in the flag-clearing sequence.
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Serial Communications Interface BYTE 1 BYTE 2 SCRF = 0 SCRF = 1 SCRF = 0 SCRF = 1 SCRF = 0 SCRF = 1 NORMAL FLAG CLEARING SEQUENCE BYTE 3 BYTE 4 READ SCS1 SCRF = 1 OR = 0 READ SCS1 SCRF = 1 OR = 0 READ SCS1 SCRF = 1 OR = 0 READ SCDR BYTE 1 READ SCDR BYTE 2 READ SCDR BYTE 3 BYTE 1 BYTE 2 SCRF = 0 OR = 0 SCRF = 1 OR = 1 SCRF = 0 OR = 1 SCRF = 1 SCRF = 1 OR = 1 DELAYED FLAG CLEARING SEQUENCE BYTE 3 BYTE 4 READ SCS1 SCRF = 1 OR = 0 READ SCS1 SCRF = 1 OR = 1 READ SCDR BYTE 1 READ SC
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Serial Communications Interface Module (SCI) 15.9.5 SCI Status Register 2 SCI status register 2 contains flags to signal the following conditions: • Break character detected • Incoming data Address: $0017 Bit 7 6 5 4 3 2 Read: 1 Bit 0 BKF RPF 0 0 Write: Reset: 0 0 0 0 0 0 = Unimplemented Figure 15-14. SCI Status Register 2 (SCS2) BKF — Break Flag Bit This clearable, read-only bit is set when the SCI detects a break character on the PTE1/RxD pin.
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Serial Communications Interface 15.9.6 SCI Data Register The SCI data register (SCDR) is the buffer between the internal data bus and the receive and transmit shift registers. Reset has no effect on data in the SCI data register. Address: $0018 Bit 7 6 5 4 3 2 1 Bit 0 Read: R7 R6 R5 R4 R3 R2 R1 R0 Write: T7 T6 T5 T4 T3 T2 T1 T0 Reset: Unaffected by reset Figure 15-15.
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Serial Communications Interface Module (SCI) 15.9.7 SCI Baud Rate Register The baud rate register (SCBR) selects the baud rate for both the receiver and the transmitter. Address: $0019 Bit 7 6 Read: Write: Reset: 0 5 4 3 2 1 Bit 0 SCP1 SCP0 R SCR2 SCR1 SCR0 0 0 0 0 0 0 R = Reserved 0 = Unimplemented Figure 15-16. SCI Baud Rate Register (SCBR) SCP1 and SCP0 — SCI Baud Rate Prescaler Bits These read/write bits select the baud rate prescaler divisor as shown in Table 15-6.
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Serial Communications Interface Table 15-7. SCI Baud Rate Selection SCR2, SCR1, and SCR0 Baud Rate Divisor (BD) 000 1 001 2 010 4 011 8 100 16 101 32 110 64 111 128 Use this formula to calculate the SCI baud rate: SCI clock source baud rate = --------------------------------------------64 × PD × BD where: SCI clock source = CGMXCLK (See 9.5.6 Crystal Output Frequency Signal (CGMXCLK).
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Serial Communications Interface Module (SCI) Table 15-8. SCI Baud Rate Selection Examples SCP1 and SCP0 Prescaler Divisor (PD) SCR2, SCR1, and SCR0 Baud Rate Divisor (BD) Baud Rate (CGMXCLK=4.
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Serial Communications Interface Technical Data 278 MC68HC908AB32 — Rev. 1.
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Technical Data — MC68HC908AB32 Section 16. Serial Peripheral Interface Module (SPI) 16.1 Contents 16.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280 16.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280 16.4 Pin Name Conventions and I/O Register Addresses . . . . . . . 281 16.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .281 16.5.1 Master Mode . . . . . . . . . . . . .
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Serial Peripheral Interface Module (SPI) 16.13.3 SPSCK (Serial Clock). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302 16.13.4 SS (Slave Select) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302 16.13.5 CGND (Clock Ground) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303 16.14 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304 16.14.1 SPI Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304 16.14.
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Serial Peripheral Interface Module (SPI) 16.4 Pin Name Conventions and I/O Register Addresses The text that follows describes the SPI. The SPI I/O pin names are SS (slave select), SPSCK (SPI serial clock), CGND (clock ground), MOSI (master out slave in), and MISO (master in/slave out). The SPI shares four I/O pins with four parallel I/O ports. The full names of the SPI I/O pins are shown in Table 16-1. The generic pin names appear in the text that follows. Table 16-1.
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Serial Peripheral Interface Module (SPI) INTERNAL BUS TRANSMIT DATA REGISTER CGMOUT ÷ 2 FROM SIM SHIFT REGISTER 7 6 5 4 3 2 1 MISO 0 ÷2 MOSI ÷8 CLOCK DIVIDER ÷ 32 RECEIVE DATA REGISTER PIN CONTROL LOGIC ÷ 128 SPMSTR SPE CLOCK SELECT SPR1 SPSCK M CLOCK LOGIC S SS SPR0 SPMSTR RESERVED MODFEN TRANSMITTER CPU INTERRUPT REQUEST RESERVED CPHA CPOL SPWOM ERRIE SPI CONTROL SPTIE SPRIE RECEIVER/ERROR CPU INTERRUPT REQUEST R SPE SPRF SPTE OVRF MODF Figure 16-2.
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Serial Peripheral Interface Module (SPI) 16.5.1 Master Mode The SPI operates in master mode when the SPI master bit, SPMSTR, is set. NOTE: Configure the SPI modules as master or slave before enabling them. Enable the master SPI before enabling the slave SPI. Disable the slave SPI before disabling the master SPI. (See 16.14.1 SPI Control Register.) Only a master SPI module can initiate transmissions. Software begins the transmission from a master SPI module by writing to the transmit data register.
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Serial Peripheral Interface Module (SPI) The SPR1 and SPR0 bits control the baud rate generator and determine the speed of the shift register. (See 16.14.2 SPI Status and Control Register.) Through the SPSCK pin, the baud rate generator of the master also controls the shift register of the slave peripheral. As the byte shifts out on the MOSI pin of the master, another byte shifts in from the slave on the master’s MISO pin. The transmission ends when the receiver full bit, SPRF, becomes set.
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Serial Peripheral Interface Module (SPI) When the master SPI starts a transmission, the data in the slave shift register begins shifting out on the MISO pin. The slave can load its shift register with a new byte for the next transmission by writing to its transmit data register. The slave must write to its transmit data register at least one bus cycle before the master starts the next transmission. Otherwise, the byte already in the slave shift register shifts out on the MISO pin.
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Serial Peripheral Interface Module (SPI) The clock phase (CPHA) control bit selects one of two fundamentally different transmission formats. The clock phase and polarity should be identical for the master SPI device and the communicating slave device. In some cases, the phase and polarity are changed between transmissions to allow a master device to communicate with peripheral slaves having different requirements.
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Serial Peripheral Interface Module (SPI) SPSCK CYCLE # FOR REFERENCE 1 2 3 4 5 6 7 8 MSB BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB SPSCK; CPOL = 0 SPSCK; CPOL =1 MOSI FROM MASTER MISO FROM SLAVE MSB SS; TO SLAVE CAPTURE STROBE Figure 16-4. Transmission Format (CPHA = 0) MISO/MOSI BYTE 1 BYTE 2 BYTE 3 MASTER SS SLAVE SS CPHA = 0 SLAVE SS CPHA = 1 Figure 16-5.
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Serial Peripheral Interface Module (SPI) 16.6.3 Transmission Format When CPHA = 1 Figure 16-6 shows an SPI transmission in which CPHA is logic 1. The figure should not be used as a replacement for data sheet parametric information. Two waveforms are shown for SPSCK: one for CPOL = 0 and another for CPOL = 1.
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Serial Peripheral Interface Module (SPI) When CPHA = 1 for a slave, the first edge of the SPSCK indicates the beginning of the transmission. This causes the SPI to leave its idle state and begin driving the MISO pin with the MSB of its data. Once the transmission begins, no new data is allowed into the shift register from the transmit data register. Therefore, the SPI data register of the slave must be loaded with transmit data before the first edge of SPSCK.
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Serial Peripheral Interface Module (SPI) WRITE TO SPDR INITIATION DELAY BUS CLOCK MOSI MSB BIT 6 1 2 BIT 5 SPSCK CPHA = 1 SPSCK CPHA = 0 SPSCK CYCLE NUMBER 3 INITIATION DELAY FROM WRITE SPDR TO TRANSFER BEGIN         WRITE TO SPDR BUS CLOCK EARLIEST LATEST WRITE TO SPDR SPSCK = INTERNAL CLOCK ÷ 2; 2 POSSIBLE START POINTS BUS CLOCK EARLIEST WRITE TO SPDR SPSCK = INTERNAL CLOCK ÷ 8; 8 POSSIBLE START POINTS LATEST SPSCK = INTERNAL CLOCK ÷ 32; 32 POSSIBLE START POINTS LATEST SPSC
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Serial Peripheral Interface Module (SPI) 16.7 Queuing Transmission Data The double-buffered transmit data register allows a data byte to be queued and transmitted. For an SPI configured as a master, a queued data byte is transmitted immediately after the previous transmission has completed. The SPI transmitter empty flag (SPTE) indicates when the transmit data buffer is ready to accept new data. Write to the transmit data register only when the SPTE bit is high.
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Serial Peripheral Interface Module (SPI) For an idle master or idle slave that has no data loaded into its transmit buffer, the SPTE is set again no more than two bus cycles after the transmit buffer empties into the shift register. This allows the user to queue up a 16-bit value to send. For an already active slave, the load of the shift register cannot occur until the transmission is completed. This implies that a back-to-back write to the transmit data register is not possible.
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Serial Peripheral Interface Module (SPI) interrupts share the same CPU interrupt vector. (See Figure 16-11.) It is not possible to enable MODF or OVRF individually to generate a receiver/error CPU interrupt request. However, leaving MODFEN low prevents MODF from being set. If the CPU SPRF interrupt is enabled and the OVRF interrupt is not, watch for an overflow condition. Figure 16-9 shows how it is possible to miss an overflow.
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Serial Peripheral Interface Module (SPI) BYTE 1 SPI RECEIVE COMPLETE BYTE 2 5 1 BYTE 3 7 BYTE 4 11 SPRF OVRF READ SPSCR 2 READ SPDR 4 6 3 1 BYTE 1 SETS SPRF BIT. 2 CPU READS SPSCR WITH SPRF BIT SET AND OVRF BIT CLEAR. CPU READS BYTE 1 IN SPDR, CLEARING SPRF BIT. 3 9 8 12 10 14 13 8 CPU READS BYTE 2 IN SPDR, CLEARING SPRF BIT. 9 CPU READS SPSCR AGAIN TO CHECK OVRF BIT. 10 CPU READS BYTE 2 SPDR, CLEARING OVRF BIT. 4 CPU READS SPSCR AGAIN TO CHECK OVRF BIT. 11 BYTE 4 SETS SPRF BIT.
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Serial Peripheral Interface Module (SPI) MODF generates a receiver/error CPU interrupt request if the error interrupt enable bit (ERRIE) is also set. The SPRF, MODF, and OVRF interrupts share the same CPU interrupt vector. (See Figure 16-11.) It is not possible to enable MODF or OVRF individually to generate a receiver/error CPU interrupt request. However, leaving MODFEN low prevents MODF from being set.
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Serial Peripheral Interface Module (SPI) slave. This happens because SS at logic 0 indicates the start of the transmission (MISO driven out with the value of MSB) for CPHA = 0. When CPHA = 1, a slave can be selected and then later unselected with no transmission occurring. Therefore, MODF does not occur since a transmission was never begun. In a slave SPI (MSTR = 0), the MODF bit generates an SPI receiver/error CPU interrupt request if the ERRIE bit is set.
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Serial Peripheral Interface Module (SPI) Reading the SPI status and control register with SPRF set and then reading the receive data register clears SPRF. The clearing mechanism for the SPTE flag is always just a write to the transmit data register. The SPI transmitter interrupt enable bit (SPTIE) enables the SPTE flag to generate transmitter CPU interrupt requests, provided that the SPI is enabled (SPE = 1).
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Serial Peripheral Interface Module (SPI) The following sources in the SPI status and control register can generate CPU interrupt requests: • SPI receiver full bit (SPRF) — The SPRF bit becomes set every time a byte transfers from the shift register to the receive data register. If the SPI receiver interrupt enable bit, SPRIE, is also set, SPRF generates an SPI receiver/error CPU interrupt request.
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Serial Peripheral Interface Module (SPI) By not resetting the SPRF, OVRF, and MODF flags, the user can still service these interrupts after the SPI has been disabled. The user can disable the SPI by writing 0 to the SPE bit. The SPI can also be disabled by a mode fault occurring in an SPI that was configured as a master with the MODFEN bit set. 16.11 Low-Power Modes The WAIT and STOP instructions put the MCU in low powerconsumption standby modes. 16.11.
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Serial Peripheral Interface Module (SPI) 16.12 SPI During Break Interrupts The system integration module (SIM) controls whether status bits in other modules can be cleared during the break state. The BCFE bit in the SIM break flag control register (SBFCR) enables software to clear status bits during the break state. (See Section 8. System Integration Module (SIM).) To allow software to clear status bits during a break interrupt, write a logic 1 to the BCFE bit.
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Serial Peripheral Interface Module (SPI) The SPI has limited inter-integrated circuit (I2C) capability (requiring software support) as a master in a single-master environment. To communicate with I2C peripherals, MOSI becomes an open-drain output when the SPWOM bit in the SPI control register is set. In I2C communication, the MOSI and MISO pins are connected to a bidirectional pin from the I2C peripheral and through a pullup resistor to VDD. 16.13.
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Serial Peripheral Interface Module (SPI) 16.13.3 SPSCK (Serial Clock) The serial clock synchronizes data transmission between master and slave devices. In a master MCU, the SPSCK pin is the clock output. In a slave MCU, the SPSCK pin is the clock input. In full-duplex operation, the master and slave MCUs exchange a byte of data in eight serial clock cycles. When enabled, the SPI controls data direction of the SPSCK pin regardless of the state of the data direction register of the shared I/O port. 16.13.
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Serial Peripheral Interface Module (SPI) When an SPI is configured as a master, the SS input can be used in conjunction with the MODF flag to prevent multiple masters from driving MOSI and SPSCK. (See 16.8.2 Mode Fault Error.) For the state of the SS pin to set the MODF flag, the MODFEN bit in the SPSCK register must be set. If the MODFEN bit is low for an SPI master, the SS pin can be used as a general-purpose I/O under the control of the data direction register of the shared I/O port.
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Serial Peripheral Interface Module (SPI) 16.14 I/O Registers Three registers control and monitor SPI operation: • SPI control register (SPCR) • SPI status and control register (SPSCR) • SPI data register (SPDR) 16.14.
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Serial Peripheral Interface Module (SPI) SPMSTR — SPI Master Bit This read/write bit selects master mode operation or slave mode operation. Reset sets the SPMSTR bit. 1 = Master mode 0 = Slave mode CPOL — Clock Polarity Bit This read/write bit determines the logic state of the SPSCK pin between transmissions. (See Figure 16-4 and Figure 16-6.) To transmit data between SPI modules, the SPI modules must have identical CPOL values. Reset clears the CPOL bit.
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Serial Peripheral Interface Module (SPI) 16.14.
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Serial Peripheral Interface Module (SPI) ERRIE — Error Interrupt Enable Bit This read/write bit enables the MODF and OVRF bits to generate CPU interrupt requests. Reset clears the ERRIE bit. 1 = MODF and OVRF can generate CPU interrupt requests 0 = MODF and OVRF cannot generate CPU interrupt requests OVRF — Overflow Bit This clearable, read-only flag is set if software does not read the byte in the receive data register before the next full byte enters the shift register.
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Serial Peripheral Interface Module (SPI) MODFEN — Mode Fault Enable Bit This read/write bit, when set to 1, allows the MODF flag to be set. If the MODF flag is set, clearing the MODFEN does not clear the MODF flag. If the SPI is enabled as a master and the MODFEN bit is low, then the SS pin is available as a general-purpose I/O. If the MODFEN bit is set, then this pin is not available as a generalpurpose I/O.
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Serial Peripheral Interface Module (SPI) 16.14.3 SPI Data Register The SPI data register consists of the read-only receive data register and the write-only transmit data register. Writing to the SPI data register writes data into the transmit data register. Reading the SPI data register reads data from the receive data register. The transmit data and receive data registers are separate registers that can contain different values. (See Figure 16-2.
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Serial Peripheral Interface Module (SPI) Technical Data 310 MC68HC908AB32 — Rev. 1.
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Technical Data — MC68HC908AB32 Section 17. Input/Output (I/O) Ports 17.1 Contents 17.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312 17.3 Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316 17.3.1 Port A Data Register (PTA) . . . . . . . . . . . . . . . . . . . . . . . . 316 17.3.2 Data Direction Register A (DDRA) . . . . . . . . . . . . . . . . . . . 316 17.4 Port B . . . . . . . . . . . . . . . . . . . . . .
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Input/Output (I/O) Ports 17.2 Introduction Fifty-one bidirectional input-output (I/O) pins form eight parallel ports. All I/O pins are programmable as inputs or outputs. NOTE: Connect any unused I/O pins to an appropriate logic level, either VDD or VSS. Although the I/O ports do not require termination for proper operation, termination reduces excess current consumption and the possibility of electrostatic damage. Addr.
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Input/Output (I/O) Ports Addr.
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Input/Output (I/O) Ports Table 17-1.
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Input/Output (I/O) Ports Table 17-1.
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Input/Output (I/O) Ports 17.3 Port A Port A is an 8-bit general-purpose bidirectional I/O port. 17.3.1 Port A Data Register (PTA) The port A data register contains a data latch for each of the eight port A pins. Address: Read: Write: $0000 Bit 7 6 5 4 3 2 1 Bit 0 PTA7 PTA6 PTA5 PTA4 PTA3 PTA2 PTA1 PTA0 Reset: Unaffected by Reset Figure 17-2. Port A Data Register (PTA) PTA[7:0] — Port A Data Bits These read/write bits are software programmable.
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Input/Output (I/O) Ports DDRA[7:0] — Data Direction Register A Bits These read/write bits control port A data direction. Reset clears DDRA[7:0], configuring all port A pins as inputs. 1 = Corresponding port A pin configured as output 0 = Corresponding port A pin configured as input NOTE: Avoid glitches on port A pins by writing to the port A data register before changing data direction register A bits from 0 to 1. Figure 17-4 shows the port A I/O logic.
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Input/Output (I/O) Ports 17.4 Port B Port B is an 8-bit special function port that shares all eight of its port pins with the analog-to-digital converter (ADC) module (see Section 14. Analog-to-Digital Converter (ADC)). 17.4.1 Port B Data Register (PTB) The port B data register contains a data latch for each of the eight port B pins.
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Input/Output (I/O) Ports 17.4.2 Data Direction Register B (DDRB) Data direction register B determines whether each port B pin is an input or an output. Writing a logic 1 to a DDRB bit enables the output buffer for the corresponding port B pin; a logic 0 disables the output buffer. Address: Read: Write: Reset: $0005 Bit 7 6 5 4 3 2 1 Bit 0 DDRB7 DDRB6 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRB0 0 0 0 0 0 0 0 0 Figure 17-6.
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Input/Output (I/O) Ports When DDRBx is a logic 1, reading address $0001 reads the PTBx data latch. When DDRBx is a logic 0, reading address $0001 reads the voltage level on the pin. The data latch can always be written, regardless of the state of its data direction bit. Table 17-3 summarizes the operation of the port B pins. Table 17-3.
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Input/Output (I/O) Ports PTC[5:0] — Port C Data Bits These read/write bits are software programmable. Data direction of each port C pin is under the control of the corresponding bit in data direction register C. Reset has no effect on port C data. MCLK — T12 System Clock The system clock is driven out of the PTC2 pin when MCLKEN is set. 17.5.2 Data Direction Register C (DDRC) Data direction register C determines whether each port C pin is an input or an output.
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Input/Output (I/O) Ports READ DDRC ($0006) INTERNAL DATA BUS WRITE DDRC ($0006) RESET DDRCx WRITE PTC ($0002) PTCx PTCx READ PTC ($0002) PTC2 ONLY MCLK MCLKEN Figure 17-10. Port C I/O Circuit When DDRCx is a logic 1, reading address $0002 reads the PTCx data latch. When DDRCx is a logic 0, reading address $0002 reads the voltage level on the pin. The data latch can always be written, regardless of the state of its data direction bit. Table 17-4 summarizes the operation of the port C pins.
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Input/Output (I/O) Ports 17.6 Port D Port D is an 8-bit special function port that shares two of its pins with the timer interface module (see Section 11. Timer Interface Module A (TIMA) and Section 12. Timer Interface Module B (TIMB)). Each port D pin has 15mA current drive (sink) and programmable pullup. 17.6.1 Port D Data Register (PTD) The port D data register contains a data latch for each of the eight port D pins.
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Input/Output (I/O) Ports 17.6.2 Data Direction Register D (DDRD) Data direction register D determines whether each port D pin is an input or an output. Writing a logic 1 to a DDRD bit enables the output buffer for the corresponding port D pin; a logic 0 disables the output buffer. Address: Read: Write: Reset: $0007 Bit 7 6 5 4 3 2 1 Bit 0 DDRD7 DDRD6 DDRD5 DDRD4 DDRD3 DDRD2 DDRD1 DDRD0 0 0 0 0 0 0 0 0 Figure 17-12.
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Input/Output (I/O) Ports When DDRDx is a logic 1, reading address $0003 reads the PTDx data latch. When DDRDx is a logic 0, reading address $0003 reads the voltage level on the pin. The data latch can always be written, regardless of the state of its data direction bit. Table 17-5 summarizes the operation of the port D pins. Table 17-5.
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Input/Output (I/O) Ports 17.7 Port E Port E is an 8-bit special function port that shares two of its pins with the timer interface module (TIMA), two of its pins with the serial communications interface module (SCI) and four of its pins with the serial peripheral interface module (SPI). 17.7.1 Port E Data Register (PTE) The port E data register contains a data latch for each of the eight port E pins.
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Input/Output (I/O) Ports MISO — Master In/Slave Out The PTE5/MISO pin is the master in/slave out terminal of the SPI module. When the SPI enable bit, SPE, is clear, the SPI module is disabled, and the PTE5/MISO pin is available for general-purpose I/O. See 16.14.1 SPI Control Register. SS — Slave Select The PTE4/SS pin is the slave select input of the SPI module. When the SPE bit is clear, or when the SPI master bit, SPMSTR, is set, the PTE4/SS pin is available for general-purpose I/O. See 16.14.
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Input/Output (I/O) Ports 17.7.2 Data Direction Register E (DDRE) Data direction register E determines whether each port E pin is an input or an output. Writing a logic 1 to a DDRE bit enables the output buffer for the corresponding port E pin; a logic 0 disables the output buffer. Address: Read: Write: Reset: $000C Bit 7 6 5 4 3 2 1 Bit 0 DDRE7 DDRE6 DDRE5 DDRE4 DDRE3 DDRE2 DDRE1 DDRE0 0 0 0 0 0 0 0 0 Figure 17-16.
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Input/Output (I/O) Ports When DDREx is a logic 1, reading address $0008 reads the PTEx data latch. When DDREx is a logic 0, reading address $0008 reads the voltage level on the pin. The data latch can always be written, regardless of the state of its data direction bit. Table 17-6 summarizes the operation of the port E pins. Table 17-6.
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Input/Output (I/O) Ports PTF[7:0] — Port F Data Bits These read/write bits are software programmable. Data direction of each port F pin is under the control of the corresponding bit in data direction register F. Reset has no effect on port F data. TACH[3:2] and TBCH[3:0] — Timer channel I/O bits The PTF5/TBCH1–PTF0/TACH2 pins are the TIMA and TIMB input capture/output compare pins.
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Input/Output (I/O) Ports NOTE: Avoid glitches on port F pins by writing to the port F data register before changing data direction register F bits from 0 to 1. Figure 17-20 shows the port F I/O logic. VDD READ DDRF ($000D) PTFPUEx INTERNAL DATA BUS WRITE DDRF ($000D) DDRFx RESET WRITE PTF ($0009) PTFx PTFx READ PTF ($0009) PTF5 to TBCH1, PTF4 to TBCH0, PTF3 to TBCH3, PTF2 to TBCH2 of TIMB PTF1 to TACH3, PTF0 to TACH2 of TIMA Figure 17-20.
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Input/Output (I/O) Ports 17.8.3 Port F Input Pullup Enable Register (PTFPUE) The port F input pullup enable register (PTFPUE) controls the input pullup device for each of the eight port F pins. Each bit is individually configurable and requires that the data direction register, DDRF, bit be configured as an input. Each pullup is automatically and dynamically disabled when a port bit’s DDRF is configured for output mode.
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Input/Output (I/O) Ports Address: Read: $000A Bit 7 6 5 4 3 0 0 0 0 0 Write: Reset: 2 1 Bit 0 PTG2 PTG1 PTG0 KBD2 KBD1 KBD0 Unaffected by reset Alternative Function: Figure 17-22. Port G Data Register (PTG) PTG[2:0] — Port G Data Bits These read/write bits are software programmable. Data direction of each port G pin is under the control of the corresponding bit in data direction register G. Reset has no effect on port G data.
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Input/Output (I/O) Ports DDRG[2:0] — Data Direction Register G Bits These read/write bits control port G data direction. Reset clears DDRG[2:0], configuring all port G pins as inputs. 1 = Corresponding port G pin configured as output 0 = Corresponding port G pin configured as input NOTE: Avoid glitches on port G pins by writing to the port G data register before changing data direction register G bits from 0 to 1. Figure 17-24 shows the port G I/O logic.
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Input/Output (I/O) Ports 17.10 Port H Port H is a 2-bit special-function port that shares all two of its pins with the keyboard interrupt (KBI) module. 17.10.1 Port H Data Register (PTH) The port H data register (PTH) contains a data latch for each of the two port H pins. Address: Read: $000B Bit 7 6 5 4 3 2 0 0 0 0 0 0 Write: Reset: 1 Bit 0 PTH1 PTH0 KBD4 KBD3 Unaffected by reset Alternative Function: Figure 17-25.
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Input/Output (I/O) Ports Address: Read: $000F Bit 7 6 5 4 3 2 0 0 0 0 0 0 0 0 0 0 0 0 Write: Reset: 1 Bit 0 DDRH1 DDRH0 0 0 Figure 17-26. Data Direction Register H (DDRH) DDRH[1:0] — Data Direction Register H Bits These read/write bits control port H data direction. Reset clears DDRH[1:0], configuring all port H pins as inputs.
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Input/Output (I/O) Ports Table 17-9. Port H Pin Functions DDRH Bit PTH Bit I/O Pin Mode Accesses to DDRH Accesses to PTH Read/Write Read Write 0 X(1) Input, Hi-Z(2) DDRH[1:0] Pin PTH[1:0](3) 1 X Output DDRH[1:0] PTH[1:0] PTH[1:0] Notes: 1. X = don’t care. 2. Hi-Z = high impedance. 3. Writing affects data register, but does not affect the input. MC68HC908AB32 — Rev. 1.
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Input/Output (I/O) Ports Technical Data 338 MC68HC908AB32 — Rev. 1.
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Technical Data — MC68HC908AB32 Section 18. External Interrupt (IRQ) 18.1 Contents 18.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339 18.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339 18.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .340 18.4.1 IRQ Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342 18.
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External Interrupt (IRQ) 18.4 Functional Description A logic 0 applied to the external interrupt pin can latch a CPU interrupt request. Figure 18-1 shows the structure of the IRQ module. Interrupt signals on the IRQ pin are latched into the IRQ latch. An interrupt latch remains set until one of the following actions occurs: • Vector fetch — A vector fetch automatically generates an interrupt acknowledge signal that clears the IRQ latch.
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External Interrupt (IRQ) NOTE: The interrupt mask (I) in the condition code register (CCR) masks all interrupt requests, including external interrupt requests. (See 8.6 Exception Control.) INTERNAL ADDRESS BUS ACK RESET TO CPU FOR BIL/BIH INSTRUCTIONS VECTOR FETCH DECODER VDD INTERNAL PULLUP VDD IRQF DEVICE D CLR Q CK IRQ SYNCHRONIZER IRQ INTERRUPT REQUEST HIGH VOLTAGE DETECT TO MODE SELECT LOGIC IRQ FF IMASK MODE Figure 18-1. IRQ Module Block Diagram Addr.
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External Interrupt (IRQ) 18.4.1 IRQ Pin A logic 0 on the IRQ pin can latch an interrupt request into the IRQ latch. A vector fetch, software clear, or reset clears the IRQ latch. If the MODE bit is set, the IRQ pin is both falling-edge-sensitive and lowlevel-sensitive. With MODE set, both of the following actions must occur to clear IRQ: • Vector fetch or software clear — A vector fetch generates an interrupt acknowledge signal to clear the latch.
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External Interrupt (IRQ) 18.5 IRQ Status and Control Register (ISCR) The IRQ Status and Control Register (ISCR) controls and monitors operation of the IRQ module.
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External Interrupt (IRQ) 18.6 IRQ Module During Break Interrupts The system integration module (SIM) controls whether the IRQ latch can be cleared during the break state. The BCFE bit in the break flag control register (BFCR) enables software to clear the latches during the break state. (See Section 8. System Integration Module (SIM).) To allow software to clear the IRQ latch during a break interrupt, write a logic 1 to the BCFE bit.
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Technical Data — MC68HC908AB32 Section 19. Keyboard Interrupt Module (KBI) 19.1 Contents 19.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345 19.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346 19.4 I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346 19.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .347 19.5.
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Keyboard Interrupt Module (KBI) 19.3 Features Features of the keyboard interrupt module include the following: Addr.
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Keyboard Interrupt Module (KBI) 19.5 Functional Description INTERNAL BUS KBD0 ACKK VDD . KBIE0 TO PULLUP ENABLE D . CLR VECTOR FETCH DECODER KEYF RESET Q SYNCHRONIZER CK . KEYBOARD INTERRUPT FF KBD4 Keyboard Interrupt Request IMASKK MODEK KBIE4 TO PULLUP ENABLE Figure 19-2. Keyboard Interrupt Block Diagram Writing to the KBIE4–KBIE0 bits in the keyboard interrupt enable register independently enables or disables the corresponding port pin as a keyboard interrupt pin.
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Keyboard Interrupt Module (KBI) • Vector fetch or software clear — A vector fetch generates an interrupt acknowledge signal to clear the interrupt request. Software may generate the interrupt acknowledge signal by writing a logic 1 to the ACKK bit in the keyboard status and control register KBSCR. The ACKK bit is useful in applications that poll the keyboard interrupt pins and require software to clear the keyboard interrupt request.
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Keyboard Interrupt Module (KBI) 19.5.1 Keyboard Initialization When a keyboard interrupt pin is enabled, it takes time for the internal pull-up to reach a logic 1. Therefore a false interrupt can occur as soon as the pin is enabled. To prevent a false interrupt on keyboard initialization: 1. Mask keyboard interrupts by setting the IMASKK bit in the keyboard status and control register. 2. Enable the KBI pins by setting the appropriate KBIEx bits in the keyboard interrupt enable register. 3.
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Keyboard Interrupt Module (KBI) Address: Read: $001B Bit 7 6 5 4 3 2 0 0 0 0 KEYF 0 Write: Reset: ACKK 0 0 0 0 0 0 1 Bit 0 IMASKK MODEK 0 0 = Unimplemented Figure 19-3. Keyboard Status and Control Register (KBSCR) Bits 7–4 — Not used These read-only bits always read as logic 0s. KEYF — Keyboard Flag Bit This read-only bit is set when a keyboard interrupt is pending. Reset clears the KEYF bit.
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Keyboard Interrupt Module (KBI) 19.5.3 Keyboard Interrupt Enable Register The keyboard interrupt enable register enables or disables the corresponding port pin to operate as a keyboard interrupt pin. Address: Read: $0021 Bit 7 6 5 0 0 0 Write: Port Pin: Reset: 0 0 0 4 3 2 1 Bit 0 KBIE4 KBIE3 KBIE2 KBIE1 KBIE0 PTH1/ KBD4 PTH0/ KBD3 PTG2/ KBD2 PTG1/ KBD1 PTG0 /KBD0 0 0 0 0 0 Figure 19-4.
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Keyboard Interrupt Module (KBI) 19.8 Keyboard Module During Break Interrupts The system integration module (SIM) controls whether the keyboard interrupt latch can be cleared during the break state. The BCFE bit in the break flag control register (BFCR) enables software to clear status bits during the break state. To allow software to clear the keyboard interrupt latch during a break interrupt, write a logic 1 to the BCFE bit.
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Technical Data — MC68HC908AB32 Section 20. Computer Operating Properly (COP) 20.1 Contents 20.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353 20.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .354 20.4 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355 20.4.1 CGMXCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .355 20.4.2 STOP Instruction . . . . .
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Computer Operating Properly (COP) 20.3 Functional Description Figure 20-1 shows the structure of the COP module. RESET CIRCUIT RESET STATUS REGISTER COP TIMEOUT CLEAR STAGES 5–12 STOP INSTRUCTION INTERNAL RESET SOURCES RESET VECTOR FETCH CLEAR ALL STAGES 12-BIT COP PRESCALER CGMXCLK COPCTL WRITE COP CLOCK COP MODULE 6-BIT COP COUNTER COPEN (FROM SIM) COP DISABLE (COPD FROM CONFIG1) RESET COPCTL WRITE CLEAR COP COUNTER COP RATE SEL (COPRS FROM CONFIG1) Figure 20-1.
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Computer Operating Properly (COP) A COP reset pulls the RST pin low for 32 CGMXCLK cycles and sets the COP bit in the SIM reset status register (SRSR). In monitor mode, the COP is disabled if the RST pin or the IRQ is held at VTST During the break state, VTST on the RST pin disables the COP. NOTE: Place COP clearing instructions in the main program and not in an interrupt subroutine.
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Computer Operating Properly (COP) 20.4.5 Internal Reset An internal reset clears the COP prescaler and the COP counter. 20.4.6 Reset Vector Fetch A reset vector fetch occurs when the vector address appears on the data bus. A reset vector fetch clears the COP prescaler. 20.4.7 COPD (COP Disable) The COPD signal reflects the state of the COP disable bit (COPD) in the configuration register 1. (See Figure 20-2.) 20.4.
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Computer Operating Properly (COP) 20.5 COP Control Register The COP control register is located at address $FFFF and overlaps the reset vector. Writing any value to $FFFF clears the COP counter and starts a new timeout period. Reading location $FFFF returns the low byte of the reset vector. Address: $FFFF Bit 7 6 5 4 3 Read: Low byte of reset vector Write: Clear COP counter Reset: Unaffected by reset 2 1 Bit 0 Figure 20-3. COP Control Register (COPCTL) 20.
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Computer Operating Properly (COP) 20.8.1 Wait Mode The COP remains active during wait mode. To prevent a COP reset during wait mode, periodically clear the COP counter in a CPU interrupt routine. 20.8.2 Stop Mode Stop mode turns off the CGMXCLK input to the COP and clears the COP prescaler. Service the COP immediately before entering or after exiting stop mode to ensure a full COP timeout period after entering or exiting stop mode.
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Technical Data — MC68HC908AB32 Section 21. Low-Voltage Inhibit (LVI) 21.1 Contents 21.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359 21.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359 21.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .360 21.4.1 Polled LVI Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361 21.4.2 Forced Reset Operation . . . . . .
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Low-Voltage Inhibit (LVI) 21.4 Functional Description Figure 21-1 shows the structure of the LVI module. The LVI is enabled out of reset. The LVI module contains a bandgap reference circuit and comparator. The LVI power bit, LVIPWRD, enables the LVI to monitor VDD voltage. The LVI reset bit, LVIRSTD, enables the LVI module to generate a reset when VDD falls below a voltage, LVITRIPF, and remains at or below that level for 9 or more consecutive CPU cycles.
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Low-Voltage Inhibit (LVI) Address: Read: $FE0F Bit 7 6 5 4 3 2 1 Bit 0 LVIOUT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Write: Reset: = Unimplemented Figure 21-2. LVI I/O Register Summary 21.4.1 Polled LVI Operation In applications that can operate at VDD levels below the LVITRIPF level, software can monitor VDD by polling the LVIOUT bit. In configuration register 1, the LVIPWRD bit must be at logic 0 to enable the LVI module, and the LVIRSTD bit must be at logic 1 to disable LVI resets.
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Low-Voltage Inhibit (LVI) 21.5 LVI Status Register (LVISR) The LVI status register flags VDD voltages below the LVITRIPF level. Address: Read: $FE0F Bit 7 6 5 4 3 2 1 Bit 0 LVIOUT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Write: Reset: = Unimplemented Figure 21-3. LVI Status Register (LVISR) LVIOUT — LVI Output Bit This read-only flag becomes set when VDD falls below the LVITRIPF voltage for 32 to 40 CGMXCLK cycles. (See Table 21-1.) Reset clears the LVIOUT bit. Table 21-1.
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Low-Voltage Inhibit (LVI) 21.7 Low-Power Modes The STOP and WAIT instructions put the MCU in low powerconsumption standby modes. 21.7.1 Wait Mode If enabled, the LVI module remains active in wait mode. If enabled to generate resets, the LVI module can generate a reset and bring the MCU out of wait mode. 21.7.2 Stop Mode If enabled in stop mode (LVISTOP set), the LVI module remains active in stop mode. If enabled to generate resets, the LVI module can generate a reset and bring the MCU out of stop mode.
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Low-Voltage Inhibit (LVI) Technical Data 364 MC68HC908AB32 — Rev. 1.
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Technical Data — MC68HC908AB32 Section 22. Break Module (BRK) 22.1 Contents 22.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365 22.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366 22.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .366 22.4.1 Flag Protection During Break Interrupts . . . . . . . . . . . . . . . 368 22.4.2 CPU During Break Interrupts . . . . . . . . . . . .
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Break Module (BRK) 22.3 Features Features of the break module include: • Accessible input/output (I/O) registers during the break interrupt • CPU-generated break interrupts • Software-generated break interrupts • COP disabling during break interrupts 22.4 Functional Description When the internal address bus matches the value written in the break address registers, the break module issues a breakpoint signal to the CPU.
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Break Module (BRK) IAB15–IAB8 BREAK ADDRESS REGISTER HIGH 8-BIT COMPARATOR IAB15–IAB0 BREAK CONTROL 8-BIT COMPARATOR BREAK ADDRESS REGISTER LOW IAB7–IAB0 Figure 22-1. Break Module Block Diagram Addr.
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Break Module (BRK) 22.4.1 Flag Protection During Break Interrupts The BCFE bit in the SIM break flag control register (SBFCR) enables software to clear status bits during the break state. 22.4.2 CPU During Break Interrupts The CPU starts a break interrupt by: • Loading the instruction register with the SWI instruction • Loading the program counter with $FFFC and $FFFD ($FEFC and $FEFD in monitor mode) The break interrupt begins after completion of the CPU instruction in progress.
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Break Module (BRK) 22.5.2 Stop Mode A break interrupt causes exit from stop mode and sets the SBSW bit in the break status register. 22.6 Break Module Registers These registers control and monitor operation of the break module: • Break status and control register (BRKSCR) • Break address register high (BRKH) • Break address register low (BRKL) • SIM Break status register (SBSR) • SIM Break flag control register (SBFCR) 22.6.
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Break Module (BRK) BRKA — Break Active Bit This read/write status and control bit is set when a break address match occurs. Writing a logic 1 to BRKA generates a break interrupt. Clear BRKA by writing a logic 0 to it before exiting the break routine. Reset clears the BRKA bit. 1 = (When read) Break address match 0 = (When read) No break address match 22.6.2 Break Address Registers The break address registers (BRKH and BRKL) contain the high and low bytes of the desired breakpoint address.
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Break Module (BRK) Address: Read: Write: Reset: $FE00 Bit 7 6 5 4 3 2 R R R R R R 0 0 0 0 0 0 R = Reserved Note: Writing a logic 0 clears SBSW. 1 SBSW Note 0 Bit 0 R 0 Figure 22-6. SIM Break Status Register (SBSR) SBSW — SIM Break Stop/Wait Bit This status bit is useful in applications requiring a return to wait or stop mode after exiting from a break interrupt. Clear SBSW by writing a logic 0 to it. Reset clears SBSW.
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Break Module (BRK) 22.6.4 SIM Break Flag Control Register The SIM break flag control register (SBFCR) contains a bit that enables software to clear status bits while the MCU is in a break state. Address: Read: Write: Reset: $FE03 Bit 7 6 5 4 3 2 1 Bit 0 BCFE R R R R R R R 0 R = Reserved Figure 22-7.
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Technical Data — MC68HC908AB32 Section 23. Electrical Specifications 23.1 Contents 23.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373 23.3 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . 374 23.4 Functional Operating Range. . . . . . . . . . . . . . . . . . . . . . . . . . 375 23.5 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375 23.6 5.0-V DC Electrical Characteristics. . . . . . .
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Electrical Specifications 23.3 Absolute Maximum Ratings Maximum ratings are the extreme limits to which the MCU can be exposed without permanently damaging it. NOTE: This device is not guaranteed to operate properly at the maximum ratings. Refer to 23.6 5.0-V DC Electrical Characteristics for guaranteed operating conditions. Characteristic(1) Symbol Value Unit Supply voltage VDD –0.3 to + 6.0 V Input voltage VIn VSS – 0.3 to VDD + 0.
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Electrical Specifications 23.4 Functional Operating Range Characteristic Symbol Operating temperature range TA –40 to +85 –40 to +125 °C VDD 5.0 ±10% 5.0 ±10% V Operating voltage range Value Unit 23.
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Electrical Specifications 23.6 5.0-V DC Electrical Characteristics Characteristic(1) Symbol Min Typ(2) Max Unit VOH VOH VOH IOH1 VDD – 0.8 VDD – 1.5 VDD – 0.8 — — — — — — — — 50 V V V mA IOH2 — — 50 mA IOHT — — 100 mA VOL VOL VOL IOL1 — — — — — — — — 0.4 1.5 1.0 50 V V V mA IOL2 — — 50 mA IOLT — — 100 mA Input high voltage All ports, IRQ, RST, OSC1 VIH 0.7 × VDD — VDD V Input low voltage All ports, IRQ, RST, OSC1 VIL VSS — 0.
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Electrical Specifications Characteristic(1) Symbol Min Typ(2) Max Unit Low-voltage inhibit reset/recover hysteresis – target HLVI 100 150 — mV POR rearm voltage(7) VPOR 0 — 200 mV POR reset voltage(8) VPORRST 0 — 800 mV RPOR 0.02 — — V/ms POR rise time ramp rate(9) Notes: 1. VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = TL to TH, unless otherwise noted 2. Typical values reflect average measurements at midpoint of voltage range, 25 °C only. 3.
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Electrical Specifications 23.8 5.0-V Control Timing Characteristic(1) Symbol Min Max Unit Frequency of operation Crystal option(2) External clock option(3) fosc 1 dc(4) 8.4 33.6 MHz MHz Internal operating frequency fBUS Note(5) 8.4 MHz RESET input pulse width low(6) tIRL 1.5 — tcyc IRQ interrupt pulse width low(7) (Edge-triggered) tILIH 1.
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Electrical Specifications 23.10 ADC Characteristics Characteristic(1) Symbol Min Max Unit Comments Supply voltage VDDAD 4.5 (VDD min) 5.5 (VDD max) V VDDAREF should be tied to the same potential as VDD via separate traces. Input voltages VADIN VREFH 0 1.5 VDDAREF VDDAREF V VADIN ≤ VREFH Resolution BAD 8 8 Bits Absolute accuracy (VREFL = 0 V, VREFH = VDDAD = 5 V ± 10%) AAD ± 1/2 ±1 LSB ADC internal clock fADIC 0.5 1.
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Electrical Specifications 23.
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Electrical Specifications SS INPUT SS PIN OF MASTER HELD HIGH 1 SPSCK OUTPUT CPOL = 0 NOTE SPSCK OUTPUT CPOL = 1 NOTE 5 4 5 4 6 MISO INPUT BITS 6–1 MSB IN 11 MOSI OUTPUT MASTER MSB OUT 7 LSB IN 10 11 BITS 6–1 MASTER LSB OUT Note: This first clock edge is generated internally, but is not seen at the SPSCK pin.
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Electrical Specifications SS INPUT 3 1 SPSCK INPUT CPOL = 0 5 4 2 SPSCK INPUT CPOL = 1 5 4 9 8 MISO INPUT SLAVE MSB OUT 6 MOSI OUTPUT BITS 6–1 7 NOTE 11 11 10 MSB IN SLAVE LSB OUT BITS 6–1 LSB IN Note: Not defined but normally MSB of character just received a) SPI Slave Timing (CPHA = 0) SS INPUT 1 SPSCK INPUT CPOL = 0 5 4 2 3 SPSCK INPUT CPOL = 1 8 MISO OUTPUT MOSI INPUT 5 4 10 NOTE 9 SLAVE MSB OUT 6 7 BITS 6–1 SLAVE LSB OUT 11 10 BITS 6–1 MSB IN LSB IN Note: Not define
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Electrical Specifications 23.12 Clock Generation Module Characteristics 23.12.1 CGM Operating Conditions Characteristic Symbol Min Typ Max Comments Operating Voltage VDD 4.5 V — 5.5 V Crystal Reference Frequency fRCLK 1 — 8.4 Module Crystal Reference Frequency fXCLK — 4.9152 MHz — Same Frequency as fRCLK Range Nominal Multiplier fNOM — 4.9152 MHz — 4.5 to 5.5 V, VDD only VCO Center-of-Range Frequency (MHz) fVRS 4.9152 — 32.0 4.5 to 5.
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Electrical Specifications 23.12.3 CGM Acquisition/Lock Time Information Description(1) Symbol Min Typ Max Notes Manual mode time to stable tACQ — (8 × VDDA)/(fXCLK × KACQ) — If CF chosen correctly tAL — (4 × VDDA)/(fXCLK × KTRK) — If CF chosen correctly Manual acquisition time tLock — tACQ+tAL — Tracking mode entry frequency tolerance DTRK 0 — ± 3.6% Acquisition mode entry frequency tolerance DUNT ± 6.3% — ± 7.2% LOCK entry freq. tolerance DLOCK 0 — ± 0.
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Electrical Specifications 23.13 FLASH Memory Characteristics Characteristic Symbol Min Max Unit — 1 — MHz FLASH read bus clock frequency fRead(1) 32k 8.
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Electrical Specifications Technical Data 386 MC68HC908AB32 — Rev. 1.
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Technical Data — MC68HC908AB32 Section 24. Mechanical Specifications 24.1 Contents 24.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387 24.3 64-Pin Plastic Quad Flat Pack (QFP) . . . . . . . . . . . . . . . . . . . 388 24.2 Introduction This section gives the dimensions for: • 64-pin plastic quad flat pack (case 840B-01) Figure 24-1 shows the latest package drawing at the time of this publication.
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Mechanical Specifications 24.3 64-Pin Plastic Quad Flat Pack (QFP) L 48 33 DETAIL A S D S H A–B V 0.20 (0.008) M B P B M L B 0.20 (0.008) –B– C A–B –A– 0.05 (0.002) A–B S D 32 S 49 –A–, –B–, –D– DETAIL A 64 17 F 1 16 –D– A 0.20 (0.008) C A–B S D S 0.05 (0.002) A–B S 0.20 (0.008) M H A–B S D S M J N E M C M H 0.02 (0.008) DATUM PLANE M C A–B S D S SECTION B–B 0.01 (0.
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Technical Data — MC68HC908AB32 Section 25. Ordering Information 25.1 Contents 25.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389 25.3 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389 25.2 Introduction This section contains ordering numbers for the MC68HC908AB32. 25.3 MC Order Numbers Table 25-1.
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Ordering Information Technical Data 390 MC68HC908AB32 — Rev. 1.
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How to Reach Us: Home Page: www.freescale.com RoHS-compliant and/or Pb- free versions of Freescale products have the functionality and electrical characteristics of their non-RoHS-compliant and/or non-Pb- free counterparts. For further information, see http://www.freescale.com or contact your Freescale sales representative. E-mail: support@freescale.com For information on Freescale.s Environmental Products program, go to http://www.freescale.com/epp.